Intel
82865G/82865GV GMCH Datasheet
89
Register Description
3.6.3
PCICMD1—PCI Command Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
04–05h
0000h
RO, R/W
16 bits
Bit
Descriptions
15:10
Reserved.
9
Fast Back-to-Back Enable (FB2B)—RO.
Hardwired to 0.
8
SERR Message Enable (SERRE)—R/W.
This bit is a global enable bit for Device 1 SERR
messaging. The GMCH communicates the SERR# condition by sending a SERR message to the
ICH5.
0 = Disable. SERR message is not generated by the GMCH for Device 1.
1 = Enable. GMCH is enabled to generate SERR messages over HI for specific Device 1 error
conditions that are individually enabled in the BCTRL1 register. The error status is reported in
the PCISTS1 register.
7
Address/Data Stepping (ADSTEP)—RO.
Hardwired to 0.
6
Parity Error Enable (PERRE)—RO.
Hardwired to 0. Parity checking is not supported on the
primary side of this device.
5
Reserved.
4
Memory Write and Invalidate Enable (MWIE)—RO.
Hardwired to 0.
3
Special Cycle Enable (SCE)—RO.
Hardwired to 0.
2
Bus Master Enable (BME)—R/W.
0 = Disable. AGP Master initiated Frame# cycles will be ignored by the GMCH. The result is a
master abort. Ignoring incoming cycles on the secondary side of the PCI-to-PCI bridge
effectively disabled the bus master on the primary side. (default)
1 = Enable. AGP master initiated Frame# cycles will be accepted by the GMCH if they hit a valid
address decode range. This bit has no affect on AGP Master originated SBA or PIPE# cycles.
1
Memory Access Enable (MAE)—R/W.
0 = Disable. All of Device 1’s memory space is disabled.
1 = Enable. Enables the memory and pre-fetchable memory address ranges defined in the
MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
0
IO Access Enable (IOAE)—R/W.
0 = Disable. All of Device 1’s I/O space is disabled.
1 = Enable. This bit must be set to1 to enable the I/O address range defined in the IOBASE1, and
IOLIMIT1 registers.