Intel
82865G/82865GV GMCH Datasheet
123
Register Description
3.8.17
MLIMIT3—Memory Limit Address Register (Device 3)
Address Offset:
Default Value:
Access:
Size:
22–23h
0000h
RO, R/W
16 bits
This register controls the processor-to-CSA non-prefetchable memory access routing based on the
following formula:
MEMORY_BASE
≤
address
≤
MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read only and return zeroes
when read. This register must be initialized by the configuration software. For the purpose of
address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be at the top of a 1-MB aligned memory block.
Note:
Memory ranges covered by the MBASE and MLIMIT registers are used to map non-prefetchable
CSA address ranges (typically, where control/status memory-mapped I/O data structures of the
graphics controller will reside) and the PMBASE and PMLIMIT registers are used to map
prefetchable address ranges (typically, graphics local memory). This segregation allows application
of USWC space attribute to be performed in a true plug-and-play manner to the prefetchable
address range for improved Processor-CSA memory access performance.
Note:
Configuration software is responsible for programming all address range registers (prefetchable,
non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with
each other and/or with the ranges covered with the main memory). There is no provision in the
GMCH hardware to enforce prevention of overlap and operations of the system in the case of
overlap are not guaranteed.
Bit
Description
15:4
Memory Address Limit (MLIMIT)—R/W.
This field corresponds to A[31:20] of the memory address
that corresponds to the upper limit of the range of memory accesses that will be passed by the
Device 3 bridge to CSA.
3:0
Reserved.