Intel
82865G/82865GV GMCH Datasheet
137
Register Description
6:4
Mode Select (SMS)—R/W.
These bits select the special operational mode of the DRAM interface.
The special modes are intended for initialization at power up. Note that FCSEN (fast CS#) must be
set to 0 while SMS cycles are performed. It is expected that BIOS may program FCSEN to
possible 1 only after initialization.
000 =Post Reset state – When the GMCH exits reset (power-up or otherwise), the mode select
field is cleared to 000.
During any reset sequence, while power is applied and reset is active, the GMCH de-asserts all
CKE signals. After internal reset is de-asserted, CKE signals remain de-asserted until this
field is written to a value different than 000. On this event, all CKE signals are asserted.
During suspend (S3, S4), GMCH internal signal triggers SDRAM controller to flush pending
commands and enter all rows into Self-Refresh mode. As part of resume sequence, the
GMCH will be reset – which clears this bit field to 000 and maintains CKE signals de-
asserted. After internal reset is de-asserted, CKE signals remain de-asserted until this field
is written to a value different than 000. On this event, all CKE signals are asserted.
001 =NOP Command Enable – All processor cycles to DRAM result in a NOP command on the
DRAM interface.
010 =All Banks Pre-charge Enable – All processor cycles to DRAM result in an “all banks
precharge” command on the DRAM interface.
011 =Mode Register Set Enable – All processor cycles to DRAM result in a “mode register” set
command on the SDRAM interface. Host address lines are mapped to SDRAM address
lines in order to specify the command sent. Host address HA[13:3] are mapped to memory
address SMA[5:1].
100 =Extended Mode Register Set Enable – All processor cycles to SDRAM result in an “extended
mode register set” command on the SDRAM interface. Host address lines are mapped to
SDRAM address lines in order to specify the command sent. Host address lines are
mapped to SDRAM address lines in order to specify the command sent. Host address
HA[13:3] are mapped to memory address SMA[5:1].
101 =Reserved
110 =CBR Refresh Enable – In this mode all processor cycles to SDRAM result in a CBR cycle on
the SDRAM interface
111 =Normal operation
3:2
Reserved
1:0
DRAM Type (DT)—RO.
This field is used to select between supported SDRAM types.
00 = Reserved
01 = Dual Data Rate SDRAM
Other = Reserved.
Bit
Description