136
Intel
82865G/82865GV GMCH Datasheet
Register Description
3.10.4
DRC—DRAM Controller Mode Register (Device 6, MMR)
Address Offset:
Default Value:
Access:
Size:
0068h–006Bh
00000001h
R/W, RO
32 bits
Bit
Description
31:30
Reserved.
29
Initialization Complete (IC)—R/W.
This bit is used for communication of the software state
between the memory controller and the BIOS.
1 = BIOS sets this bit to 1 after initialization of the DRAM memory array is complete.
28:23
Reserved.
22:21
Number of Channels (CHAN)—R/W.
The GMCH memory controller supports three modes of
operation. When programmed for single-channel mode, there are three options: channel A is
populated, channel B is populated, or both are populated but not identically. When both channels
have DIMMs installed and they are not identical (from channel to channel), the controller operates
in a mode that is referred to as virtual single-channel. In this mode, the two physical channels are
not in lock step but act as one logical channel. To operate in either dual-channel mode, the two
channels must be populated identically.
00 = Single-channel or virtual single-channel
01 = Dual-channel, linear organization
10 = Dual-channel, tiled organization
11 = Reserved
20:11
Reserved
10:8
Refresh Mode Select (RMS)—R/W.
This field determines whether refresh is enabled and, if so, at
what rate refreshes will be executed.
000 = Reserved
001 = Refresh enabled. Refresh interval 15.6 μsec
010 = Refresh enabled. Refresh interval 7.8 μsec
011 = Refresh enabled. Refresh interval 64 μsec
111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode)
Other = Reserved
7
Reserved.