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| 型号： | ADE7569ASTZF16 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 108/136页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER MCU 16K 64LQFP |
| 标准包装： | 1 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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ADE7566/ADE7569
Table 116. RTC Configuration SFR (TIMECON, 0xA1)
Preliminary Technical Data
Bit No.
7
Mnemonic
MIDNIGHT
Default
0
Description
Midnight Flag. This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by the user to
indicate that the midnight event has been serviced. In twenty-four hour mode, the midnight flag is
raised once a day at midnight.
6
TFH
0
Twenty-Four Hour Mode. This bit is retained during a watchdog reset or an external reset. It is reset after
a power on reset (POR).
TFH Result
0 256-Hour Mode. The HOUR register rolls over from 255 to 0.
1 24-Hour Mode. The HOUR register rolls over from 23 to 0.
5 to 4
ITS[1:0]
0
Interval Timer Time-Base Selection.
ITS[1:0] Result (Time base)
00 1/128 sec.
01 Second.
10 Minute.
11 Hour.
3
SIT
0
Interval Timer 1 Time Alarm.
SIT Result
0 The ALARM flag is set after INTVAL counts and then another interval count starts.
1 The ALARM flag is set after one time interval.
2
ALARM
0
Interval Timer Alarm Flag. This bit is set when the configured time interval has elapsed. It can be cleared
by the user to indicate that the alarm event has been serviced. This bit cannot be set to 1 by user code.
1
ITEN
0
Interval Timer Enable.
ITEN Result
0 The interval timer is disabled. The 8-bit interval timer counter is reset.
1
Set this bit to enable the interval timer. The RTCEN bit must also be set to enable the
interval timer.
0
RTCEN
1
RTC Enable. Also Temperature, Battery and Supply ADC Background Strobe Enable. Note that the RTC is
always enabled.
Table 117. Hundredths of a Second Counter SFR (HTHSEC, 0xA2)
Bit No.
7 to 0
Mnemonic
HTHSEC
Default
0
Description
This counter updates every 1/128 sec, referenced from the calibrated 32 kHz clock. It overflows from
127 to 00, incrementing the seconds counter (SEC). This register is retained during a watchdog reset or
an external reset. It is reset after a POR.
Table 118. Seconds Counter SF R (SEC, 0xA3)
Bit No.
7 to 0
Mnemonic
SEC
Default
0
Description
This counter updates every second, referenced from the calibrated 32 kHz clock. It overflows from 59 to 00,
incrementing the minutes counter (MIN). This register is retained during a watchdog reset or an external
reset. It is reset after a POR.
Table 119. Minutes Counter SF R (MIN, 0xA4)
Bit No.
7 to 0
Mnemonic
MIN
Default
0
Description
This counter updates every minute, referenced from the calibrated 32 kHz clock. It overflows from 59 to 00,
incrementing the hours counter, HOUR. This register is retained during a watchdog reset or an external
reset. It is reset after a POR.
Table 120. Hours Counter SFR (HOUR, 0xA5)
Bit No.
7 to 0
Mnemonic
HOUR
Default
0
Description
This counter updates every hour, referenced from the calibrated 32 kHz clock. If the TFH bit in the RTC
Configuration SFR (TIMECON, 0xA1) is set, the HOUR SFR overflows from 23 to 00, setting the MIDNIGHT
bit and creating a pending RTC interrupt. If the TFH bit is cleared, the HOUR SFR overflows from 255 to 00,
setting the MIDNIGHT bit and creating a pending RTC interrupt. This register is retained during a
watchdog reset or an external reset. It is reset after a POR.
Rev. PrA | Page 108 of 136
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