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参数资料
型号： ADE7569ASTZF16
厂商： Analog Devices Inc
文件页数： 70/136页
文件大小： 0K
描述： IC ENERGY METER MCU 16K 64LQFP
标准包装： 1
输入阻抗： *
测量误差： *
电压 - 高输入/输出： *
电压 - 低输入/输出： *
电流 - 电源： *
电源电压： *
测量仪表类型： *
工作温度： *
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-LQFP（10x10）
包装： 托盘

ADE7566/ADE7569
8052 MCU CORE ARCHITECTURE
Preliminary Technical Data
The ADE7566/ADE7569 have an 8052 MCU core and use the
8051 instruction set. Some of the standard 8052 peripherals,
such as the UART, have been enhanced. This section describes
the standard 8052 core and its enhancements used in the
ADE7566/ADE7569.
The special function register (SFR) space is mapped into the
upper 128 bytes of internal data memory space and is accessed
by direct addressing only. It provides an interface between the
CPU and all on-chip peripherals. A block diagram showing the
programming model of the ADE7566/ADE7569 via the SFR
area is shown in Figure 67.
All registers except the program counter (PC), instruction
256 BYTES
GENERAL
PURPOSE
RAM
STACK
REGISTER
BANKS
16kB ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE
PROGRAM/DATA
MEMORY
8051
COMPATIBLE
CORE
PC IR
256 BYTES XRAM
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
ENERGY
MEASUREMENT
POWER
MANAGEMENT
RTC
LCD DRIVER
TEMPERATURE
ADC
BATTERY
ADC
OTHER ON-CHIP
PERIPHERALS:
SERIAL I/O
WDT
TIMERS
register (IR), and the four general-purpose register banks
reside in the SFR area. The SFR registers include power
control, configuration, and data registers that provide an
interface between the CPU and all on-chip peripherals.
MCU REGISTERS
The registers used by the MCU are summarized in this section.
Table 52. 8051 SFRs
Figure 67. ADE7566/ADE7569 Block Diagram
SFR
A
B
PSW
PCON
DPL
DPH
DPTR
SP
CFG
Address
0xE0
0xF0
0xD0
0x87
0x82
0x83
0x83 and 0x82
0x81
0xAF
Bit Addressable
Yes
Yes
Yes
No
No
No
No
No
No
Description
Accumulator.
Auxiliary Math Register.
Program Status Word (see Table 53).
Power Control Register (see Table 54).
Data Pointer LSByte (see Table 55).
Data Pointer MSByte (see Table 56).
16-Bit Data Pointer (see Table 57).
Stack Pointer LSByte (see Table 58).
Configuration (see Table 59).
Table 53. Program Status Word SFR (PSW, 0xD0)
Bit No.
7
6
5
4 to 3
Address
0xD7
0xD6
0xD5
0xD4, 0xD3
Mnemonic
CY
AC
F0
RS1, RS0
Description
Carry Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
Auxiliary Carry Flag. Modified by ADD and ADDC instructions.
General-Purpose Flag Available to the User.
Register Bank Select Bits.
RS1 RS0 Result (Selected Bank)
0 0 0
0 1 1
1 0 2
1 1 3
2
1
0
0xD2
0xD1
0xD0
OV
F1
P
Overflow Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
General-Purpose Flag Available to the User.
Parity Bit. The number of bits set in the accumulator added to the value of the parity bit is always an
even number.
Rev. PrA | Page 70 of 136
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