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参数资料
型号： ADE7569ASTZF16
厂商： Analog Devices Inc
文件页数： 62/136页
文件大小： 0K
描述： IC ENERGY METER MCU 16K 64LQFP
标准包装： 1
输入阻抗： *
测量误差： *
电压 - 高输入/输出： *
电压 - 低输入/输出： *
电流 - 电源： *
电源电压： *
测量仪表类型： *
工作温度： *
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-LQFP（10x10）
包装： 托盘
ADE7566/ADE7569
Apparent Energy Pulse Output
All the ADE7566/ADE7569 circuitry has a pulse output whose
frequency is proportional to apparent power (see the Energy-to-
Frequency Conversion section). This pulse frequency output
uses the calibrated signal after VAGAIN. This output can also
be used to output a pulse whose frequency is proportional to I rms .
The pulse output is active low and should preferably be connected
to an LED as shown in Figure 66.
Line Apparent Energy Accumulation
The ADE7566/ADE7569 are designed with a special apparent
energy accumulation mode that simplifies the calibration process.
By using the on-chip, zero-crossing detection, the
ADE7566/ADE7569 accumulate the apparent power signal in
the LVAHR register for an integral number of half cycles, as shown
in Figure 64. The line apparent energy accumulation mode is
always active.
The number of half-line cycles is specified in the LINCYC
register, which is an unsigned 16-bit register. The ADE7566/
ADE7569 can accumulate apparent power for up to 65,535
combined half cycles. Because the apparent power is integrated
on the same integral number of line cycles as the line active
register and reactive energy register, these values can easily be
compared. The energies are calculated more accurately because
of this precise timing control and provide all the information
needed for reactive power and power factor calculation.
At the end of an energy calibration cycle, the CYCEND flag in
the Interrupt Status Register 3 SFR (MIRQSTH, 0xDE) is set. If
the CYCEND enable bit in the Interrupt Enable Register 3 SFR
(MIRQENH, 0xDB) is enabled, the 8052 core has a pending
ADE interrupt.
As for LWATTHR, when a new half-line cycles is written
in LINCYC register, the LVAHR register is reset and a new
accumulation start at the next zero-crossing. The number of
half-line cycles is then counted until LINCYC is reached.
This implementation provides a valid measurement at the first
CYCEND interrupt after writing to the LINCYC register. The
line apparent energy accumulation uses the same signal path as
Preliminary Technical Data
the apparent energy accumulation. The LSB size of these two
registers is equivalent.
Apparent Power No-Load Detection
The ADE7566/ADE7569 include a no-load threshold feature on
the apparent power that eliminates any creep effects in the meter.
The ADE7566/ADE7569 accomplish this by not accumulating
energy if the multiplier output is below the no-load threshold.
When the apparent power is below the no-load threshold, the
VANOLOAD flag in the Interrupt Status Register 1 SFR
(MIRQSTL, 0xDC) is set. If the VANOLOAD bit is set in the
Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), the 8052
core has a pending ADE interrupt. The ADE interrupt stays
active until the APNOLOAD status bit is cleared (see the
Energy Measurement Interrupts section).
The no-load threshold level is selectable by setting the
VANOLOAD bits in the NLMODE Register (0x0E). Setting
these bits to 0b00 disables the no-load detection and setting
them to 0b01, 0b10, or 0b11 set the no-load detection threshold
to 0.030%, 0.015%, and 0.0075% of the full-scale output
frequency of the multiplier, respectively.
This no-load threshold can also be applied to the I rms pulse
output when selected. In this case, the level of no-load threshold
is the same as for the apparent energy.
AMPERE-HOUR ACCUMULATION
In case of a tampering situation where no voltage is available to
the energy meter, the ADE7566/ADE7569 is capable of accumu-
lating the ampere-hour instead of apparent power into the VAHR,
RVAHR, and LVAHR registers. When Bit 3 (VARMSCFCON) of
the MODE2 Register (0x0C) is set, the VAHR, RVAHR, LVAHR,
and the input for the digital-to-frequency converter accumulate
I rms instead of apparent power. All the signal processing and
calibration registers available for apparent power and energy
accumulation remain the same when ampere-hour accumulation is
selected. However, the scaling of I rms and apparent power
require different values for gain calibration in the VAGAIN,
VADIV, CFxNUM and CFxDEN registers.
APPARENT POWER
or Irms
%
+
+
48
0
VADIV[7:0]
LVAHR REGISTER IS
UPDATED EVERY LINCYC
ZERO CROSSING WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
FROM
VOLTAGE CHANNEL
ADC
LPF1
ZERO-CROSSING
DETECTION
CALIBRATION
CONTROL
23
LVAHR [23:0]
0
LINCYC [15:0]
Figure 64. Line Cycle Apparent Energy Accumulation
Rev. PrA | Page 62 of 136
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