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参数资料
型号： ADE7569ASTZF16
厂商： Analog Devices Inc
文件页数： 63/136页
文件大小： 0K
描述： IC ENERGY METER MCU 16K 64LQFP
标准包装： 1
输入阻抗： *
测量误差： *
电压 - 高输入/输出： *
电压 - 低输入/输出： *
电流 - 电源： *
电源电压： *
测量仪表类型： *
工作温度： *
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-LQFP（10x10）
包装： 托盘
Preliminary Technical Data
ENERGY-TO-FREQUENCY CONVERSION
The ADE7566/ADE7569 also provide two energy-to-frequency
conversions for calibration purposes. After initial calibration at
manufacturing, the manufacturer or end customer often verify
the energy meter calibration. One convenient way to do this is
for the manufacturer to provide an output frequency that is
proportional to the active power, reactive power, apparent power,
or I rms under steady load conditions. This output frequency can
provide a simple, single-wire, optically isolated interface to external
calibration equipment. Figure 65 illustrates the energy-to-
frequency conversion in the ADE7566/ADE7569.
MODE2 REGISTER 0x0C
VARMSCFCON CFxSEL[1:0]
ADE7566/ADE7569
is proportional to I rms , and CF1 cannot be proportional to
apparent power apparent power if CF2 is proportional to I rms .
Pulse Output Characteristic
The pulse output for both DFCs stays low for 90 ms if the pulse
period is longer than 180 ms (5.56 Hz). If the pulse period is
shorter than 180 ms, the duty cycle of the pulse output is 50%.
The pulse output is active low and should preferably be
connected to an LED as shown on Figure 66.
V DD
CF
I rms
CFxNUM
Figure 66. CF Pulse Output
The maximum output frequency with ac input signals at
VA
VAR
DFC
÷
CFx PULSE
OUTPUT
full scale and CFxNUM = 0x00 and CFxDEN = 0x00 is
approximately 21.1 kHz.
WATT
CFxDEN
The ADE7566/ADE7569 incorporate two registers per DFC,
CFxNUM[15:0] and CFxDEN[15:0], to set the CFx frequency.
Figure 65. Energy-to-Frequency Conversion
Two digital-to-frequency converters (DFC) are used to generate
the pulsed outputs. When WDIV = 0 or 1, the DFC generates a
pulse each time 1 LSB in the energy register is accumulated. An
output pulse is generated when CFxNUM/CFxDEN number of
pulses are generated at the DFC output. Under steady load
conditions, the output frequency is proportional to the active
power, reactive power, apparent power or I rms , depending on the
CFxSEL bits in the MODE2 Register (0x0C).
Both pulse outputs can be enabled or disabled by clearing or
setting Bit DISCF1 and Bit DISCF2 in the MODE1 Register
(0x0B), respectively.
Both pulse outputs set separate flags in the Interrupt Status
Register 2 SFR (MIRQSTM, 0xDD), CF1 and CF2. If the CF1
and CF2 enable bits in the Interrupt Enable Register 2 SFR
(MIRQENM, 0xDA) are set, the 8052 core has a pending ADE
interrupt. The ADE interrupt stays active until the CF1 or CF2
status bits are cleared (see the Energy Measurement Interrupts
section).
Pulse Output Configuration
The two pulse output circuits have separate configuration bits
These are unsigned 16-bit registers that can be used to adjust
the CFx frequency to a wide range of values. These frequency
scaling registers are 16-bit registers that can scale the output
frequency by 1/2 16 to 1 with a step of 1/2 16 .
If the value 0 is written to any of these registers, the value 1
would be applied to the register. The ratio CFxNUM/CFxDEN
should be less than 1 to ensure proper operation. If the ratio of
the registers CFxNUM/CFxDEN is greater than 1, the register
values are adjusted to a ratio of 1. For example, if the output
frequency is 1.562 kHz while the contents of CFxDEN are 0
(0x000), the output frequency can be set to 6.1 Hz by writing
0xFF to the CFxDEN register.
ENERGY REGISTER SCALING
The ADE7566/ADE7569 provide measurements of active,
reactive, and apparent energies that use separate paths and
filtering for calculation. The difference in data paths can result
in small differences in LSB weight between active, reactive, and
apparent energy registers. These measurements are internally
compensated so the scaling is nearly one to one. The
relationship between these registers is show in Table 43.
Table 43. Energy Registers Scaling
in the MODE2 Register (0x0C). Setting the CFxSEL bits to
0b00, 0b01, or 0b1x configure the DFC to create a pulse output
proportional to active power, reactive power (not available in
the ADE7566), or apparent power/I rms , respectively.
The selection between I rms and apparent power is done by the
Line Frequency = 50 Hz
VAR = 0.9952 × WATT
VA = 0.9978 × WATT
VAR = 0.9997 × WATT
VA = 0.9977 × WATT
Line Frequency = 60 Hz
VAR = 0.9949 × WATT
VA = 1.0015 × WATT
VAR = 0.9999 × WATT
VA = 1.0015 × WATT
Integrator
Off
Off
On
On
VARMSCFCON bit in the MODE2 Register (0x0C). With this
selection, CF2 cannot be proportional to apparent power if CF1
Rev. PrA | Page 63 of 136
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