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参数资料
型号： ADE7569ASTZF16
厂商： Analog Devices Inc
文件页数： 66/136页
文件大小： 0K
描述： IC ENERGY METER MCU 16K 64LQFP
标准包装： 1
输入阻抗： *
测量误差： *
电压 - 高输入/输出： *
电压 - 低输入/输出： *
电流 - 电源： *
电源电压： *
测量仪表类型： *
工作温度： *
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-LQFP（10x10）
包装： 托盘
ADE7566/ADE7569
Table 46. Temperature and Supply Delta SFR (DIFFPROG, 0xF3)
Preliminary Technical Data
Bit No.
7 to 6
5 to 3
Mnemonic
Reserved
TEMP_DIFF[2:0]
Default
0
0
Description
Reserved.
Difference threshold between last temperature measurement interrupting 8052 and new
temperature measurement that should interrupt 8052.
TEMP_DIFF[2:0] Result
000 No interrupt
001 1 LSB (≈ 0.8°C)
010 2 LSB (≈ 1.6°C)
011 3 LSB (≈ 2.4°C)
100 4 LSB (≈ 3.2°C)
101 5 LSB (≈ 4°C)
110 6 LSB (≈ 4.8°C)
111 Every temperature measurement
2 to 0
VDCIN_DIFF[2:0]
0
Difference threshold between last external voltage measurement interrupting 8052 and new
external measurement that should interrupt 8052.
VDCIN_DIFF[2:0] Result
000 No interrupt
001 1 LSB (≈ 120 mV)
010 2 LSB (≈ 240 mV)
011 3 LSB (≈ 360 mV)
100 4 LSB (≈ 480 mV)
101 5 LSB (≈ 600 mV)
110 6 LSB (≈ 720 mV)
111 Every V DCIN measurement
Table 47. Start ADC Measurement SFR (ADCGO, 0xD8)
Bit No.
7
Address
0xDF
Mnemonic
PLLACK
Default
0
Description
Set this bit to clear the PLL fault bit, PLL_FLT, in the PERIPH register. A PLL fault is
generated if a reset was caused because the PLL lost lock.
6 to 3
2
0xDE to 0xDB
0xDA
Reserved
VDCIN_ADC_GO
0
0
Reserved.
Set this bit to initiate an external voltage measurement. This bit is cleared when
the measurement request is received by the ADC.
1
0xD9
TEMP_ADC_GO
0
Set this bit to initiate a temperature measurement. This bit is cleared when the
measurement request is received by the ADC.
0
0xD8
BATT_ADC_GO
0
Set this bit to initiate a battery measurement. This bit is cleared when the
measurement request is received by the ADC.
Table 48. Battery Detection Threshold SFR (BATVTH, 0xFA)
Bit No.
7 to 0
Mnemonic
BATVTH
Default
0
Description
The battery ADC value is compared to this register, the battery threshold register. If BATADC is
lower than the threshold, an interrupt is generated.
Table 49. VDCIN ADC Value SFR (VDCINADC, 0xEF)
Bit No.
7 to 0
Mnemonic
VDCINADC
Default
0
Description
The V DCIN ADC value in this register is updated when an ADC interrupt occurs.
Table 50. Battery ADC Value SFR (BATADC, 0xDF)
Bit No.
7 to 0
Mnemonic
BATADC
Default
0
Description
The battery ADC value in this register is updated when an ADC interrupt occurs.
Table 51. Temperature ADC Value SFR (TEMPADC, 0xD7)
Bit No.
7 to 0
Mnemonic
TEMPADC
Default
0
Description
The temperature ADC value in this register is updated when an ADC interrupt occurs.
Rev. PrA | Page 66 of 136
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