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参数资料
型号： ADE7569ASTZF16
厂商： Analog Devices Inc
文件页数： 115/136页
文件大小： 0K
描述： IC ENERGY METER MCU 16K 64LQFP
标准包装： 1
输入阻抗： *
测量误差： *
电压 - 高输入/输出： *
电压 - 低输入/输出： *
电流 - 电源： *
电源电压： *
测量仪表类型： *
工作温度： *
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-LQFP（10x10）
包装： 托盘
Preliminary Technical Data
UART OPERATION MODES
Mode 0 (Shift Register with Baud Rate Fixed at f CORE /12)
ADE7566/ADE7569
All of the following conditions must be met at the time the final
shift pulse is generated to receive a character:
Mode 0 is selected when the SM0 and SM1 bits in the Serial
Communications Control Register Bit Description SFR (SCON,
0x98) are cleared. In this shift register mode, serial data enters
and exits through RxD. TxD outputs the shift clock. The baud
rate is fixed at f CORE /12. Eight data bits are transmitted or
?
?
If the extended UART is disabled (EXTEN = 0 in the CFG
SFR), RI must be 0 to receive a character. This ensures that
the data in the SBUF SFR is not overwritten if the last
received character has not been read.
If frame error checking is enabled by setting SM2, the
received.
Transmission is initiated by any instruction that writes to the
Serial Port Buffer SFR (SBUF, 0x99). The data is shifted out of
the RxD line. The 8 bits are transmitted with the least significant
bit (LSB) first.
Reception is initiated when the receive enable bit (REN) is 1
and the receive interrupt bit (RI) is 0. When RI is cleared, the
received stop bit must be set to receive a character. This
ensures that every character received comes from a valid
frame, with both a start bit and a stop bit.
If any of these conditions are not met, the received frame is
irretrievably lost, and the receive interrupt flag (RI) is not set.
If the received frame has met the previous criteria, the following
events occur:
data is clocked into the RxD line, and the clock pulses are
output from the TxD line as shown in Figure 89.
?
The 8 bits in the receive shift register are latched into the
SBUF SFR.
RxD
(DATA OUT)
TxD
(SHIFT CLOCK)
DATA BIT 0
DATA BIT 1
DATA BIT 6
DATA BIT 7
?
?
The ninth bit (stop bit) is clocked into RB8 in the SCON SFR.
The receiver interrupt flag (RI) is set.
Figure 89. 8-Bit Shift Register Mode
Mode 1 (8-Bit UART, Variable Baud Rate)
Mode 1 is selected by clearing SM0 and setting SM1. Each data
byte (LSB first) is preceded by a start bit (0) and followed by a
stop bit (1). Therefore, each frame consists of 10 bits transmitted
on TxD or received on RxD.
The baud rate is set by a timer overflow rate. Timer 1 or Timer 2
can be used to generate baud rates, or both timers can be used
simultaneously where one generates the transmit rate and the
other generates the receive rate. There is also a dedicated timer
for baud rate generation, the UART timer, which has a fractional
divisor to precisely generate any baud rate (see the UART Timer
Generated Baud Rates section).
Transmission is initiated by a write to the Serial Port Buffer SFR
(SBUF, 0x99) Next, a stop bit (1) is loaded into the ninth bit
position of the transmit shift register. The data is output bit-by-
bit until the stop bit appears on TxD and the transmit interrupt
flag (TI) is automatically set as shown in Figure 90.
Mode 2 (9-Bit UART with Baud Fixed at f CORE /64 or f CORE /32)
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode, the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at f CORE /64 by default, although setting the
SMOD bit in the Program Control SFR (PCON, 0x87) doubles
the frequency to f CORE /32. Eleven bits are transmitted or received:
a start bit (0), 8 data bits, a programmable ninth bit, and a stop
bit (1). The ninth bit is most often used as a parity bit or as part
of a multiprocessor communication protocol, although it can be
used for anything, including a ninth data bit, if required.
To use the ninth data bit as part of a communication protocol for
a multiprocessor network such as RS-485, the ninth bit is set to
indicate that the frame contains the address of the device that
the master would like to communicate with. The devices on the
network are always listening for a packet with the ninth bit set
and are configured such that if the ninth bit is cleared, the frame
is not valid, and a receive interrupt is not generated. If the ninth
bit is set, all devices on the network receive the address and obtain a
receive character interrupt. The devices examine the address and if
TxD
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
STOP BIT
it matches one of the device’s preprogrammed address, that device
configures itself to listen to all incoming frames, even those with
TI
(SCON.1)
SET INTERRUPT
(FOR EXAMPLE,
READY FOR MORE DATA)
Figure 90. 8-Bit Variable Baud Rate
Reception is initiated when a 1-to-0 transition is detected on
the ninth bit cleared. Because the master has initiated commu-
nication with that device, all the following packets with the
ninth bit cleared are intended specifically for that addressed
device until another packet with the ninth bit set is received. If
the address does not match, the device continues to listen for
address packets.
RxD. Assuming that a valid start bit is detected, character
reception continues. The 8 data bits are clocked into the serial
port shift register.
Rev. PrA | Page 115 of 136
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