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参数资料
| 型号： | ADE7569ASTZF16 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 48/136页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER MCU 16K 64LQFP |
| 标准包装： | 1 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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ADE7566/ADE7569
PHASE COMPENSATION
The ADE7566/ADE7569 must work with transducers that can
have inherent phase errors. For example, a phase error of 0.1° to
Preliminary Technical Data
RMS CALCULATION
The root mean square (rms) value of a continuous signal V(t) is
defined as
∫
0.3° is not uncommon for a current transformer (CT). These
phase errors can vary from part to part, and they must be
corrected to perform accurate power calculations. The errors
associated with phase mismatch are particularly noticeable at
V rms =
1
T
T
× V 2 ( t ) dt
0
(3)
low power factors. The ADE7566/ADE7569 provide a means of
digitally calibrating these small phase errors. The part allows a
small time delay or time advance to be introduced into the
signal processing chain to compensate for small phase errors.
Because the compensation is in time, this technique should only
be used for small phase errors in the range of 0.1° to 0.5°.
Correcting large phase errors using a time shift technique can
introduce significant phase errors at higher harmonics.
For time sampling signals, rms calculation involves squaring the
signal, taking the average, and obtaining the square root. The
ADE7566/ADE7569 implement this method by serially squaring
the input, averaging them, and then taking the root square of
the average. The averaging part of this signal processing is done
by implementing a low-pass filter (LPF3 in Figure 47, Figure 48
Figure 49). This LPF has a ?3dB cut-off frequency of 2 Hz when
MCLK = 4.096 MHz.
The phase calibration register (PHCAL[7:0]) is a twos complement,
signed, single-byte register that has values ranging from 0x82
(?126d) to 0x68 (104d).
The PHCAL register is centered at 0x40, meaning that writing
V ( t ) = 2 × V sin( ω t )
where V is the rms voltage.
V 2 ( t ) = V 2 ? V 2 cos ( 2 ω t )
(4)
(5)
0x40 to the register gives 0 delay. By changing this register, the
time delay in the voltage channel signal path can change from
?231.93 μs to +48.83 μs (MCLK = 4.096 MHz). One LSB is
equivalent to 1.22 μs (MCLK/5) time delay or advance. A line
frequency of 60 Hz gives a phase resolution of 0.026° at the
fundamental (that is, 360° × 1.22 μs × 60 Hz).
When this signal goes through LPF3, the cos(2 ω t) term is attenu-
ated and only the DC term V rms2 goes through (see Figure 47).
V 2 ( t ) = V 2 – V 2 cos (2 ω t )
V ( t ) = √ 2 × V sin( ω t )
LPF3
Figure 46 illustrates how the phase compensation is used to
remove a 0.1° phase lead in current channel due to the external
INPUT
V
transducer. To cancel the lead (0.1°) in current channel, a phase
lead must also be introduced into voltage channel. The resolution
of the phase adjustment allows the introduction of a phase lead
in increments of 0.026°. The phase lead is achieved by introducing
a time advance into voltage channel. A time advance of 4.88 μs
is made by writing ?4 (0x3C) to the time delay block, thus
reducing the amount of time delay by 4.88 μs, or equivalently, a
phase lead of approximately 0.1° at a line frequency of 60 Hz
(0x3C represents ?4 because the register is centered with 0 at 0x40).
V 2 ( t ) = V 2
Figure 47. RMS Signal Processing
The rms signals can be read from the waveform register by
setting the WAVMODE Register (0x0D) and setting the WFSM
bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB).
Like the current and voltage channels waveform sampling
modes, the waveform date is available at sample rates of
27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS.
I AP
HPF
24
It is important to note that when the current input is larger than
I
PGA1
ADC 1
40% of full scale, the I rms waveform sample register does not
I N
24
LPF2
represent the true processed rms value. The rms value processed
with this level of input is larger than the 24-bit read by the wave-
V
V P
V N
PGA2
ADC 2
1
7
DELAY BLOCK
1.22μs/LSB
0
CHANNEL 2 DELAY
REDUCED BY 4.48μs
(0.1°LEAD AT 60Hz)
0x0B IN PHCAL[7:0]
V
form register, making the value read truncated on the high end.
V
1 0 0 1 0 1 1 1
I
I
0.1°
PHCAL[7:0]
–231.93μs TO +48.83μs
60Hz
60Hz
Figure 46. Phase Calibration
Rev. PrA | Page 48 of 136
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相关代理商/技术参数 |
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| ADE7569ASTZF162 | 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver |
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| ADE7751 | 制造商:AD 制造商全称:Analog Devices 功能描述:Energy Metering IC with On-Chip Fault Detection |
| ADE7751AAN-REF | 制造商:AD 制造商全称:Analog Devices 功能描述:Energy Metering IC with On-Chip Fault Detection |
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