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参数资料
| 型号： | ADE7569ASTZF16 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 85/136页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER MCU 16K 64LQFP |
| 标准包装： | 1 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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Preliminary Technical Data
WATCHDOG TIMER
The watchdog timer generates a device reset or interrupt within
a reasonable amount of time if the ADE7566/ADE7569 enter an
erroneous state, possibly due to a programming error or electrical
noise. The watchdog is enabled by default with a timeout of 2 sec
and creates a system reset if not cleared within 2 sec. The watchdog
function can be disabled by clearing the watchdog enable bit
(WDE) in the Watchdog Timer SFR (WDCON, 0xC0).
The watchdog circuit generates a system reset or interrupt
(WDS) if the user program fails to set the WDE bit within a
predetermined amount of time (set by the PRE[3:0] bits).
The watchdog timer is clocked from the 32.768 kHz external
crystal connected between the CLKIN and CLKOUT pins.
ADE7566/ADE7569
The WDCON SFR can be written only by user software if the
double write sequence described in Table 71 is initiated on
every write access to the WDCON SFR.
To prevent any code from inadvertently disabling the watchdog, a
watchdog protection can be activated. This watchdog protection
locks in the watchdog enable and event settings so they cannot
be changed by user code. The protection is activated by clearing
a watchdog protection bit in the flash memory. The watchdog
protection bit is the most significant bit at Address 0x3FFA of
the flash memory. When this bit is cleared, the WDIR bit is forced
to 0, and the WDE bit is forced to 1. Note that the sequence for
configuring the flash protection bits must be followed to modify
the watchdog protection bit at Address 0x3FFA (see the
Protecting the Flash section).
Table 71. Watchdog Timer SFR (WDCON, 0xC0)
Bit No.
7 to 4
Address
0xC7 to
Mnemonic
PRE[3:0]
Default
7
Description
Watchdog Prescaler. In normal mode, the 16-bit watchdog timer is clocked by the input
0xC4
clock (32.768 kHz). The PREx bits set which of the upper bits of the counter are used as the
watchdog output following:
t WATCHDOG = 2 PRE ×
2 9
CLKIN
PRE[3:0] Result (Watchdog timeout)
0000 15.6 ms
0001 31.2 ms
0010 62.5 ms
0011 125 ms
0100 250 ms
0101 500 ms
0110 1 sec
0111 2 sec
1000 0, Automatic reset
1001 0, Serial download reset
1010 to 1111 Not a valid selection
3
0xC3
WDIR
0
Watchdog Interrupt Response Bit. When cleared, the watchdog generates a system reset
when the watchdog time out period has expired. When set, the watchdog generates a
interrupt when the watchdog time out period has expired.
2
0xC2
WDS
0
Watchdog Status Bit. This bit is set to indicate that a watchdog timeout has occurred. It is cleared
by writing a 0 or by an external hardware reset. A watchdog reset will not clear WDS; therefore, it
can be used to distinguish between a watchdog reset and a hardware reset from the RESET pin.
1
0xC1
WDE
1
Watchdog Enable Bit. When set, this bit enables the watchdog and clears its counter. The
watchdog counter is subsequently cleared again whenever WDE is set. If the watchdog is
not cleared within its selected timeout period, it generates a system reset or watchdog
interrupt, depending on the WDIR bit.
0
0xC0
WDWR
0
Watchdog Write Enable Bit. See the Writing to the Watchdog Timer SFR (WDCON, 0xC0)
section.
Rev. PrA | Page 85 of 136
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