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| 型号： | ADE7569ASTZF16 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 90/136页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER MCU 16K 64LQFP |
| 标准包装： | 1 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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ADE7566/ADE7569
Table 82. LCD Pointer SFR (LCDPTR, 0xAC)
Preliminary Technical Data
Bit No.
7
Mnemonic
W/R
Default
0
Description
Read or Write LCD Bit. If this bit is set (1), the data in LCDDAT is written to the address indicated by the
LCDPTR[5:0] bits.
6
5 to 0
RESERVED
ADDRESS
0
0
Reserved.
LCD Memory Address (see Table 85).
Table 83. LCD Data SFR (LCDDAT, 0xAE)
Bit No.
7 to 0
Mnemonic
LCDDATA
Default
0
Description
Data to be written into or read out of the LCD Memory SFRs.
Table 84. LCD Segment Enable 2 SFR (LCDSEGE2, 0xED)
Bit No.
7 to 4
3
2
1
0
Mnemonic
RESERVED
FP19EN
FP18EN
FP17EN
FP16EN
Default
0
0
0
0
0
Description
Reserved.
FP19 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function.
FP18 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function.
FP17 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function.
FP16 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function.
1
Not within the range of typical LCD frame rates.
LCD SETUP
The LCD Configuration SFR (LCDCON, 0x95) configures the
LCD module to drive the type of LCD in the user end system.
The BIAS and LMUX[1:0] bits in this SFR should be set according
to the LCD specifications.
The COM2/FP28 and COM3/FP27 pins default to LCD segment
lines. Selecting the 3× multiplex level in the LCD Configuration
SFR (LCDCON, 0x95) by setting LMUX[1:0] to 2d changes the
FP28 pin functionality to COM2. The 4× multiplex level selection,
LMUX[1:0] = 3d, changes the FP28 pin functionality to COM2
and the FP27 pin functionality to COM3.
LCD segments FP0 to FP15 and FP26 are enabled by default.
Additional pins are selected for LCD functionality in the LCD
Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment
Enable 2 SFR (LCDSEGE2, 0xED) where there are individual
enable bits for segment pins FP16 to FP25. The LCD pins do
not have to be enabled sequentially. For example, if the alternate
function of FP23, the Timer 2 input, is required, any of the
other shared pins, FP16 to FP25, can be enabled instead.
The Display Element Control section contains details about
setting up the LCD data memory to turn individual LCD
segments on and off. Setting the LCDRST bit in the LCD
Configuration SFR (LCDCON, 0x95) resets the LCD data
memory to its default (0). A power-on reset also clears the
LCD data memory.
LCD TIMING AND WAVEFORMS
An LCD segment acts like a capacitor that is charged and
discharged at a certain rate. This rate, the refresh rate, determines
the visual characteristics of the LCD. A slow refresh rate results
in the LCD blinking on and off in between refreshes. A fast
refresh rate presents a screen that appears to be continuously lit
up. In addition, a faster refresh rate consumes more power.
The frame rate, or refresh rate, for the LCD module is derived
from the LCD clock, f LCDCLK . The LCD clock is selected as 2048 Hz
or 128 Hz by the CLKSEL bit in the LCD Configuration SFR
(LCDCON, 0x95). The minimum refresh rate needed for the
LCD to appear solid (without blinking) is independent of the
multiplex level.
The LCD waveform frequency, f LCD , is the frequency at which
the LCD switches which common line is active. Thus, the LCD
waveform frequency depends heavily on the multiplex level.
The frame rate and LCD waveform frequency are set by f LCDCLK ,
the multiplex level, and the FD[3:0] frame rate selection bits in
the LCD Clock SFR (LCDCLK, 0x96).
The LCD module provides 16 different frame rates for
f LCDCLK = 2048 Hz, ranging from 8 Hz to 128 Hz for an
LCD with 4× multiplexing. Fewer options are available
with f LCDCLK = 128 Hz, ranging from 8 Hz to 32 Hz for a
4× multiplexed LCD. The 128 Hz clock is beneficial for
battery operation because it consumes less power than the
2048 Hz clock. The frame rate is set by the FD[3:0] bits in the
LCD Clock SFR (LCDCLK, 0x96); see Table 79 and Table 80.
The LCD waveform is inverted at twice the LCD waveform
frequency, f LCD . This way, each frame has an average DC offset
of zero. ADC offset degrades the lifetime and performance of
the LCD.
Rev. PrA | Page 90 of 136
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