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参数资料
型号： ADE7569ASTZF16
厂商： Analog Devices Inc
文件页数： 117/136页
文件大小： 0K
描述： IC ENERGY METER MCU 16K 64LQFP
标准包装： 1
输入阻抗： *
测量误差： *
电压 - 高输入/输出： *
电压 - 低输入/输出： *
电流 - 电源： *
电源电压： *
测量仪表类型： *
工作温度： *
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-LQFP（10x10）
包装： 托盘
Preliminary Technical Data
Timer 2 is selected as the baud rate generator by setting TCLK
f CORE
ADE7566/ADE7569
FRACTIONAL ÷(1 + SBAUDF/64)
and/or RCLK in Timer/Counter 2 Control SFR (T2CON, 0xC8).
The baud rates for transmit and receive can be simultaneously
different. Setting RCLK and/or TCLK puts Timer 2 into its baud
DIVIDER
TIMER 1/TIMER 2
Tx CLOCK
TIMER 1/TIMER 2
Rx CLOCK
rate generator mode as shown in Figure 92.
In this case, the baud rate is given by the following formula:
÷2 DIV + SBTH
1
0
Rx CLOCK
UARTBAUDEN
Tx CLOCK
Mode 1 and Mode 3 Baud Rate =
f CORE
( 16 × [ 65536 ? ( RCAP 2 H : RCAP 2 L ) ] )
UART Timer Generated Baud Rates
The high integer dividers in a UART block mean that high speed
baud rates are not always possible. In addition, generating baud
rates requires the exclusive use of a timer, rendering it unusable
for other applications when the UART is required. To address
this problem, each ADE7566/ADE7569 has a dedicated baud
rate timer (UART timer) specifically for generating highly
accurate baud rates. The UART timer can be used instead of
Timer 1 or Timer 2 for generating very accurate high speed
UART baud rates, including 115,200 bps. This timer also allows
a much wider range of baud rates to be obtained. In fact, every
1 0
÷32
UART TIMER
Rx/Tx CLOCK
Figure 91. UART Timer, UART Baud Rate
Two SFRs, Enhanced Serial Baud Rate Control SFR (SBAUDT,
0x9E) and UART Timer Fractional Divider SFR (SBAUDF,
0x9D), are used to control the UART timer. SBAUDT is the
baud rate control SFR; it sets up the integer divider (DIV) and
the extended divider (SBTH) for the UART timer.
The appropriate value to write to the DIV[2:0] and SBTH[1:0]
bits can be calculated using the following formula where f CORE is
defined in the POWCON SFR (see
Table 23). Note that the DIV value must be rounded down to
the nearest integer.
? ?
log ?
?
? 16 × Baud Rate ?
desired bit rate from 12 bps to 393,216 bps can be generated to
within an error of ±0.8%. The UART timer also frees up the other
three timers, allowing them to be used for different applications.
A block diagram of the UART timer is shown in Figure 91.
DIV + SBTH =
? ?
f CORE
log ( 2 )
TIMER 1
OVERFLOW
2
0
1
f CORE
C/ T2 = 0
CONTROL
TL2
(8 BITS)
TH2
(8 BITS)
TIMER 2
OVERFLOW
1
0
SMOD
RCLK
T2
PIN
C/ T2 = 1
TR2
1
0
16
TCLK
Rx
CLOCK
NOTE: AVAILABILITY OF ADDITIONAL
EXTERNAL INTERRUPT
RCAP2L
RCAP2H
RELOAD
16
Tx
CLOCK
T2EX
PIN
TRANSITION
DETECTOR
CONTROL
EXF 2
TIMER 2
INTERRUPT
EXEN2
Figure 92. Timer 2, UART Baud Rates
Rev. PrA | Page 117 of 136
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