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参数资料
| 型号： | ADE7569ASTZF16 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/136页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER MCU 16K 64LQFP |
| 标准包装： | 1 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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ADE7566/ADE7569
Preliminary Technical Data
Pin No.
43
44
45
46
47
48
49, 50
51
52, 53
54
55
56
57
58
59
60
61
62
63
64
Mnemonic
P0.2/CF1/RTCCAL
SDEN/P2.3
BCTRL/INT1/P0.0
XTAL2
XTAL1
INT0
V P, V N
EA
I P , I N
AGND
FP26
RESET
REF IN/OUT
V BAT
V INTA
V DD
V SWOUT
V INTD
DGND
V DCIN
Description
General-Purpose Digital I/O Port 0.2. / Calibration Frequency Logic Output. The CF1 logic output gives
instantaneous active, reactive, or apparent power information / RTC Calibration Frequency Logic Output.
The RTCCAL logic output gives access to the calibrated RTC output.
This pin is used to enable serial download mode through a resistor when pulled low on power-up or reset.
On reset, this pin momentarily becomes an input and the status of the pin is sampled. If there is no pull-
down resistor in place, the pin momentarily goes high and then user code is executed. If a pull-down resistor
is in place, the embedded serial download/debug kernel executes and this pin remains low during internal
program execution. / General-Purpose Digital I/O Port 2.3.
Digital Input for Battery Control. This logic input connects V DD or V BAT to V SW internally when set to logic high
or low, respectively. When left open, the connection between V DD or V BAT and V SW is selected internally.
/ External Interrupt Input. / General-Purpose Digital I/O Port 0.0.
A crystal can be connected across this pin and XTAL1 (see XTAL1 description below) to provide a clock
source for the ADE7566/ADE7569. The XTAL2 pin can drive one CMOS load when an external clock is
supplied at XTAL1 or by the gate oscillator circuit.
An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be
connected across XTAL1 and XTAL2 to provide a clock source for the ADE7566/ADE7569. The clock
frequency for specified operation is 32.768 kHz.
Interrupt Input.
Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
This pin is used as an input for emulation. When held high, this input enables the device to fetch code from
internal program memory locations. The ADE7566/ADE7569 do not support external code memory. This pin
should not be left floating.
Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
This pin provides the ground reference for the analog circuitry.
LCD Segment Output 26.
Reset Input, Active Low.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
1.2 V ± 8% and a typical temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled with
a 1 μF capacitor in parallel with a ceramic 100 nF capacitor.
3.3 V Power Supply Input from the Battery. This pin is connected internally to V DD when the battery is
selected as the power supply for the ADE7566/ADE7569.
This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
3.3 V Power Supply Input from the Regulator. This pin is connected internally to V DD when the regulator is
selected as the power supply for the ADE7566/ADE7569. This pin should be decoupled with a 10 μF
capacitor in parallel with a ceramic 100 nF capacitor.
3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the
ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF
capacitor.
This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
This pin provides the ground reference for the digital circuitry.
Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is 3.3 V with respect to
AGND. This pin is used to monitor the pre-regulated dc voltage.
Rev. PrA | Page 18 of 136
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