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| 型号： | ADE7569ASTZF16 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 126/136页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER MCU 16K 64LQFP |
| 标准包装： | 1 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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ADE7566/ADE7569
Table 142. I 2 C Slave Address SF R (I2CADR, 0xE9)
Preliminary Technical Data
Bit No.
7 to 1
0
Mnemonic
I2CSLVADR
I2CR_W
Default
0
0
Description
Address of the I 2 C Slave Being Addressed. Writing to this register starts the I 2 C transmission (read or write).
Command Bit for Read or Write. When this bit is set to Logic 1, a read command is transmitted on the I 2 C
bus. Data from slave in the SPI2CRx SFR is expected after command byte. When this bit is set to Logic 0, a
write command is transmitted on the I 2 C bus. Data to slave is expected in the SPI2CTx SFR.
Table 143. I 2 C Interrupt Status Register SFR (SPI2CSTAT, 0xEA)
Bit No.
7
6
Mnemonic
I2CBUSY
I2CNOACK
Default
0
0
Description
This bit is set to Logic 1 when the I 2 C interface is used. When set, the Tx FIFO is emptied
I 2 C No Acknowledgement Transmit Interrupt. This bit is set to Logic 1 when the slave device
does not send an acknowledgement. The I 2 C communication is stopped after this event.
Write a 0 to this bit to clear it.
5
I2CRxIRQ
0
I 2 C Receive Interrupt. This bit is set to Logic 1 when the receive FIFO is not empty.
Write a 0 to this bit to clear it.
4
I2CTxIRQ
0
I 2 C Transmit Interrupt. This bit is set to Logic 1 when the transmit FIFO is empty.
Write a 0 to this bit to clear it.
3 to 2
I2CFIFOSTAT[1:0]
0
Status Bits for 3- or 4-Bytes Deep I 2 C FIFO. The FIFO monitored in these 2 bits is the one currently
used in I 2 C communication (receive or transmit) because only one FIFO is active at a time.
I2CFIFOSTAT[1:0] Result
00 FIFO empty
01 Reserved
10 FIFO half full
11 FIFO full
1
0
I2CACC_ERR
I2CTxWR_ERR
0
0
Set when trying to write and read at the same time. Write a 0 to this bit to clear it.
Set when write was attempted when I 2 C transmit FIFO was full. Write a 0 to this bit to clear it.
READ AND WRITE OPERATIONS
Figure 98 and Figure 99 depict I 2 C read and write operations, respectively. Note that the LSB of the I2CADR register is used to select
whether a read or write operation is performed on the slave device. During the read operation, the master acknowledges are generated
automatically by the I 2 C peripheral. The master generated NACK before the end of a read operation is also automatically generated after
the I2CRCT, Bits[4:0] bits have been read from the slave. If the I2CADR register is updated during a transmission, instead of generating a
stop at the end of the read or write operation, the master generates a start condition and continues with the next communication.
Reading the SPI/I 2 C Receive Buffer SFR (SPI2CRx, 0x9B)
Reading the SPI2CRx SFR should be done with a 2-cycle instruction, such as
Mov a, spi2crx or Mov R0, spi2crx .
A 3-cycle instruction such as
Mov 3dh, spi2crx
will not transfer the right data into RAM Address 0x3d.
1
9
1
9
1
9
SCLK
SDATA
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK BY
SLAVE
FRAME 2
DATA BYTE 1 FROM MASTER
ACK BY
MASTER
FRAME N + 1
DATA BYTE N FROM SLAVE
NACK BY STOP BY
MASTER MASTER
Figure 98. I 2 C Read Operation
1
9
1
9
SCLK
SDATA
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK BY
SLAVE
FRAME 2
DATA BYTE 1 FROM MASTER
ACK BY
SLAVE
STOP BY
MASTER
Figure 99. I 2 C Write Operation
Rev. PrA | Page 126 of 136
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