参数资料
型号: ADE7569ASTZF16
厂商: Analog Devices Inc
文件页数: 61/136页
文件大小: 0K
描述: IC ENERGY METER MCU 16K 64LQFP
标准包装: 1
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
Preliminary Technical Data
APPARENT ENERGY CALCULATION
The apparent energy is given as the integral of the apparent power.
ADE7566/ADE7569
provided to read the apparent energy. This register is reset to 0
after a read operation
Apparent Energy = ∫ Apparent Power ( t ) dt
(33)
Note that the apparent energy register is unsigned. By setting the
VAEHF and VAEOF bits in the Interrupt Enable Register 2 SFR
Apparent Energy = Lim ? ∑ ApparentPo wer ( nT ) × T ? (34)
The ADE7566/ADE7569 achieve the integration of the apparent
power signal by continuously accumulating the apparent power
signal in an internal 48-bit register. The apparent energy register
(VAHR[23:0]) represents the upper 24 bits of this internal
register. This discrete time accumulation or summation is
equivalent to integration in continuous time. Equation 34
expresses the relationship.
? ∞ ?
T → 0 ? n = 0 ?
where:
n is the discrete time sample number.
T is the sample period.
The discrete time sample period (T) for the accumulation
register in the ADE7566/ADE7569 is 1.22 μs (5/MCLK).
Figure 63 shows this discrete time integration or accumulation.
The apparent power signal is continuously added to the internal
register. This addition is a signed addition even if the apparent
(MIRQENM, 0xDA), the ADE7566/ADE7569 can be configured
to issue an ADE interrupt to the 8052 core when the apparent
energy register is half-full or when an overflow occurs. The half-full
interrupt for the unsigned apparent energy register is based on
24 bits as opposed to 23 bits for the signed active energy register.
Integration Times Under Steady Load
As mentioned in the Apparent Energy Calculation section, the
discrete time sample period (T) for the accumulation register is
1.22 μs (5/MCLK). With full-scale sinusoidal signals on the
analog inputs and the VAGAIN register set to 0x000, the
average word value from the apparent power stage is 0x1A36E2
(see the Apparent Power Calculation section). The maximum
value that can be stored in the apparent energy register before it
overflows is 2 24 or 0xFF,FFFF. The average word value is added
to the internal register, which can store 2 48 or 0xFFFF,FFFF,FFFF
before it overflows. Therefore, the integration time under these
conditions with VADIV = 0 is calculated as follows:
Time =
energy theoretically remains positive.
The 49 bits of the internal register are divided by VADIV. If the
0xFFFF, FFFF, FFFF
0xD055
× 1 . 22 μ s = 199 sec = 3 . 33 min
(35)
value in the VADIV register is 0, the internal apparent energy
register is divided by 1. VADIV is an 8-bit unsigned register.
When VADIV is set to a value different from 0, the integration
time varies, as shown in Equation 36.
The upper 24 bits are then written in the 24-bit apparent energy
register (VAHR[23:0]). The RVAHR register (24 bits long) is
Time = Time WDIV = 0 × VADIV
(36)
23
VAHR[23:0]
0
48
VADIV
%
0
APPARENT POWER
or
Irms
+
+
48
0
T
APPARENT
POWER SIGNAL = P
APPARENT POWER OR Irms IS
ACCUMULATED (INTEGRATED)
IN THE APPARENT ENERGY
REGISTER
TIME (nT)
Figure 63. Apparent Energy Calculation
Rev. PrA | Page 61 of 136
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