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参数资料
| 型号： | ADE7569ASTZF16 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 125/136页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER MCU 16K 64LQFP |
| 标准包装： | 1 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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Preliminary Technical Data
I 2 C COMPATIBLE INTERFACE
The ADE7566/ADE7569 support a fully licensed I 2 C interface.
ADE7566/ADE7569
The bit rate is defined in the I2CMOD SFR as follows:
The I 2 C interface is implemented as a full hardware master.
SDATA is the data I/O pin, and SCLK is the serial clock. These
f SCLK =
f CORE
16 × 2 I 2 CR [ 1 : 0 ]
two pins are shared with the MOSI and SCLK pins of the on-chip
SPI interface. Therefore, the user can enable only one interface
or the other on these pins at any given time. The SCPS bit in the
Configuration SFR (CFG, 0xAF) selects which peripheral is
active.
The two pins used for data transfer, SDATA and SCLK, are
configured in a wire-AND format that allows arbitration in a
SLAVE ADDRESSES
The I 2 C Slave Address SFR (I2CADR, 0xE9) contains the slave
device ID. The LSB of this register contains a read/write request.
A write to this SFR starts the I 2 C communication.
I 2 C SFR REGISTER LIST
The I 2 C peripheral interface consists of five SFRs:
The transfer sequence of a I C system consists of a master device
multimaster system.
2
initiating a transfer by generating a start condition while the bus
is idle. The master transmits the address of the slave device and
the direction of the data transfer in the initial address transfer. If
?
?
?
?
?
I2CMOD
SPI2CSTAT
I2CADR
SPI2CTx
SPI2CRx
the slave acknowledges, the data transfer is initiated. This continues
until the master issues a stop condition and the bus becomes idle.
SERIAL CLOCK GENERATION
The I 2 C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (256 kHz) or standard mode (32 kHz).
Table 140. I 2 C SFR Register List
Because the SPI and I 2 C serial interfaces share the same pins,
they also share the same SFRs, such as the SPI2CTx and SPIXCRx
SFRs. In addition, the I2CMOD, I2CADR, SPI2CSTAT, and
SPI2CTx SFRs are shared with the SPIMOD1, SPIMOD2, and
SPISTAT SFRs, respectively.
SFR Address
0x9A
0x9B
0xE8
0xE9
0xEA
Name
SPI2CTx
SPI2CRx
I2CMOD
I2CADR
SPI2CSTAT
R/W
W
R
R/W
R/W
R/W
Length
8
8
8
8
8
Default
0
0
0
0
Description
SPI/I 2 C Data out Register (see Table 134).
SPI/I 2 C Data in Register (see Table 135).
I 2 C Configuration Register (see Table 141).
I 2 C Configuration Register (see Table 142).
SPI/I 2 C Interrupt Status Register (see Table 143).
Table 141. I 2 C Mode Register SFR (I2CMOD, 0xE8)
Bit No.
7
Address
0xEF
Mnemonic
I2CEN
Default
0
Description
I 2 C Enable Bit. When this bit is set to Logic 1, the I 2 C interface is enabled. A write to the
I2CADR SFR starts a communication.
6 to 5
0xEE to 0xED
I2CR[1:0]
0
I 2 C SCLK Frequency.
I2CR[1:0] Result
00 f CORE /16 = 256 kHz if f CORE = 4.096 MHz
01 f CORE /32 = 128 kHz if f CORE = 4.096 MHz
10 f CORE /64 = 64 Hz if f CORE = 4.096 MHz
11 f CORE /128= 32 kHz if f CORE = 4.096 MHz
4 to 0
0xEC to 0xE8
I2CRCT[4:0]
0
Configures the length of the I 2 C received FIFO buffer. The I 2 C peripheral stops when
I2CRCT, Bit[4:0] + 1 byte have been read or if an error has occurred.
Rev. PrA | Page 125 of 136
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