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参数资料
| 型号： | ADE7569ASTZF16 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 86/136页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER MCU 16K 64LQFP |
| 标准包装： | 1 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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ADE7566/ADE7569
Preliminary Technical Data
Writing to the Watchdog Timer SFR (WDCON, 0xC0)
Writing data to the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the following instruction must
be a write instruction to the WDCON SFR.
Disable Watch dog
CLR EA
SETB WDWR
CLR WDE
SETB EA
This sequence is necessary so that the WDCON SFR is protected from code execution upsets that might unintentionally modify this SFR.
Interrupts should be disabled during this operation due to the consecutive instruction cycles.
Table 72. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA)
Bit No.
7
Mnemonic
WDPROT_PROTKY7
Default
1
Description
This bit holds the protection for the Watchdog timer and the 7 th bit of the flash protection key.
When this bit is cleared, the watchdog enable and event, selected by WDE and WDIR cannot be
changed by user code. The watchdog configuration is then fixed to WDIR=0 and WDE=1. The
watchdog timeout in PRE[3:0] can still be modified by user code.
The value of this bit is also used to set the Flash protection key. If this bit is cleared to protect the
watchdog, then the default value for the Flash protection key is 0x7F instead of 0xFF (see the
Protecting the Flash section for more information on how to clear this bit).
7 to 0
PROTKY[7:0]
0xFF
These bits hold the flash protection key. The content of this Flash address is compared to the
Flash Protection Key SFR (PROTKY, 0xBB) when the protection is being set or changed. If the two
values match, the new protection is written to the Flash addresses 0x3FFF to 0x3FFB. see the
Protecting the Flash section for more information on how to configure these bits.
Watchdog Timer Interrupt
If the watchdog timer is not cleared within the watchdog timeout
period, a system reset occurs unless the watchdog timer interrupt
is enabled. The watchdog timer interrupt enable bit (WDIR) is
Note that WDIR is automatically configured as a high priority
interrupt. This interrupt cannot be disabled by the EA bit in the
IE register. Even if all of the other interrupts are disabled, the
watchdog is kept active to watch over the program.
located in the Watchdog Timer SFR (WDCON, 0xC0). Enabling
the WDIR bit allows the program to examine the stack or other
variables that may have led the program to execute inappropriate
code. The watchdog timer interrupt also allows the watchdog to
be used as a long interval timer.
Rev. PrA | Page 86 of 136
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相关代理商/技术参数 |
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