参数资料
型号: ADE7569ASTZF16
厂商: Analog Devices Inc
文件页数: 28/136页
文件大小: 0K
描述: IC ENERGY METER MCU 16K 64LQFP
标准包装: 1
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
ADE7566/ADE7569
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE7566/ADE7569 can be configured to generate a PSM
interrupt when the source of V SW changes from V DD to V BAT ,
indicating battery switchover. Setting the EBSO bit in the Power
Management Interrupt Enable SFR (IPSME, 0xEC) enables this
event to generate a PSM interrupt.
The ADE7566/ADE7569 can also be configured to generate an
interrupt when the source of V SW changes from V BAT to V DD ,
indicating that the V DD power supply has been restored. Setting
the EPSR bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
The flags in the Power Management Interrupt Flag SFR (IPSMF,
0xF8) for these interrupts, FBSO and FPSR, are set regardless of
whether the respective enable bits have been set. The battery
switchover and power supply restore event flags, FBSO and FPSR,
are latched. These events must be cleared by writing a 0 to these
bits. Bit 6 in the Peripheral Configuration SFR (PERIPH, 0xF4),
VSWSOURCE, tracks the source of V SW . The bit is set when V SW
is connected to V DD and cleared when V SW is connected to V BAT .
V DCIN ADC PSM Interrupt
The ADE7566/ADE7569 can be configured to generate a PSM
interrupt when V DCIN changes magnitude by more than a
configurable threshold. This threshold is set in the Temperature
and Supply Delta SFR (DIFFPROG, 0xF3). See the External
Voltage Measurement section for more information. Setting the
EVDCIN bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
The V DCIN voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to
check the change in V DCIN . Conversions can also be initiated by
writing to the Start ADC Measurement SFR (ADCGO, 0xD8).
Preliminary Technical Data
See the External Voltage Measurement section for details on
how V DCIN is measured.
V BAT Monitor PSM Interrupt
The V BAT voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to
check the change in V BAT . The FBAT bit is set when the battery
level is lower than the threshold set in the Battery Detection
Threshold SFR (BATVTH, 0xFA) or when a new measurement
is ready in the Battery ADC Value SFR (BATADC, 0xDF). See
the Battery Measurement section for more information. Setting
the EBAT bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
V DCIN Monitor PSM Interrupt
The V DCIN voltage is monitored by a comparator. The FVDCIN
bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8)
is set when the V DCIN input level is lower than 1.2 V. Setting the
EVDCIN bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
This event, which is associated with the SAG monitoring, can
be used to detect a power supply (V DD ) being compromised and
to trigger further actions prior to deciding a switch of V DD to V BAT .
SAG Monitor PSM Interrupt
The ADE7566/ADE7569 energy measurement DSP monitors
the ac voltage input at the V P and V N input pins. The SAGLVL
register is used to set the threshold for a line voltage SAG event.
The FSAG bit in the Power Management Interrupt Flag SFR
(IPSMF, 0xF8) is set if the line voltage stays below the level set
in the SAGLVL register for the number of line cycles set in the
SAGCYC register. See the Line Voltage Sag Detection section
for more information. Setting the ESAG bit in the Power
Management Interrupt Enable SFR (IPSME, 0xEC) enables this
event to generate a PSM interrupt.
The FVDCIN flag indicates when a V DCIN measurement is ready.
Rev. PrA | Page 28 of 136
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