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参数资料
| 型号： | DSRT-L030-011 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, XMA |
| 文件页数： | 10/86页 |
| 文件大小： | 667K |
| 代理商： | DSRT-L030-011 |
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RipTide PCI Audio/Comm Device Family Product Description
18
ROCKWELL PROPRIETARY INFORMATION
1167
4.2.3
Serial PnP EEPROM Interface
Signal
Type
Level
I
OL/IOH
Reset
State
Std.
Load
Description
SEEPCS
Ot4
TTL
4mA
L
20pF
Serial EEPROM Chip Select. Connect to EEPROM: CS. Leave
open if EEPROM is not installed.
SEEPCLK
Ot4
TTL
4mA
L
20pF
Serial EEPROM Clock. Connect to EEPROM: SK. Leave open if
EEPROM is not installed.
SEEPDI
It
TTL
Serial EEPROM Data In from EEPROM. Connect to EEPROM:
DO. Connect to GND if EEPROM is not installed.
SEEPDO
Ot4
TTL
4mA
L
20pF
Serial EEPROM Data Out to EEPROM. Connect to EEPROM: DI.
Leave open if EEPROM is not installed.
4.2.4
JTAG Port Interface
Signal
Type
Level
I
OL/IOH
Reset
State
Std.
Load
Description
TCK
It
TTL
Test Clock. This signal is used during boundary scan testing to
clock serial data.
TDI
Itpu
TTL
Test Input. The signal contains serial data that is shifted in on the
rising edge of TCK. This pin has an internal pull up.
TDO
Ot4
TTL
4mA
Z
20pF
Test Output. This tristateable signal contains serial data that is
shifted out on the falling edge of TCK.
TMS
Itpu
TTL
Test Mode Select. This signal controls the operation of the TAP
controller. This pin has an internal pull up.
TRST#
Itpu
TTL
Test Reset. A high to low signal forces the TAP controller into a
logic reset state. Must be held low during normal (non-test)
operation. This pin has an internal pullup.
4.2.5
AC link Interface
Signal
Type
Level
I
OL/IOH
Reset
State
Std.
Load
Description
BIT_CLK
Iacl
ACL
Bit Clock. 12.288 MHz AC-link bit clock. Connect to Codec
BIT_CLK output.
SYNC
Oacl4
ACL
4mA
L
50pF
Frame Sync. 48 kHz fixed rate sample AC-link sync. Connect to
Codec SYNC input and to docking station Codec SYNC input.
SDATA_IN
Iacl
ACL
Serial Data Input. Serial, time division multiplexed, AC-link input
data stream. Connect to Codec SDATA_IN output.
SDATA_OUT
Oacl4
ACL
4mA
L
50pF
Serial Data Output. Serial, time division multiplexed, AC-link output
stream. Connect to Codec SDATA_OUT input.
RESET#
Oacl4
ACL
4mA
L
50pF
Reset. Active low reset output. Connect to Codec RESET# input.
BIT_CLKD
Iacl
ACL
Bit Clock for Docking Station. 12.288 MHz AC-link bit clock.
Connect to docking station Codec BIT_CLK output. Connect to
GND if docking station Codec is not installed.
SDATA_IND
Iacl
ACL
Serial Data Input for Docking Station. Serial, time division
multiplexed, AC-link input data stream. Connect to docking station
Codec SDATA_IN output. Connect to GND if docking station Codec
is not installed.
RESETD#
Oacl4
ACL
4mA
L
50pF
Reset for Docking Station. Active low reset output. Connect to
docking station Codec RESET# input. Leave open if docking station
Codec is not installed.
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