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| 型号： | DSRT-L030-011 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, XMA |
| 文件页数： | 64/86页 |
| 文件大小： | 667K |
| 代理商： | DSRT-L030-011 |
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RipTide PCI Audio/Comm Device Family Product Description
1167
ROCKWELL PROPRIETARY INFORMATION
67
15 Clock Generation
The Controller receives two external clocks. The PCICLK signal (normally 33 MHz) provides clocking to all of the PCI
interface and Modem DMA/Interface Controller (MDIC) portions of the design. The BIT_CLK (12.288 MHz) signal provides
clocking for the remainder of the Controller. The Controller also provides the 28.224 MHz clock signal for the optional Modem
DSP. Therefore, only the Codec requires connection to an external crystal circuit.
When the attached AMC’97 codec is placed into its slowest power state (PR4 asserted), the BIT_CLK provided to the
Controller will stop. A number of methods can be used to resume normal operations when in PR4 state.
Issue a GRESET from the host
Change docking state
Cycle PCI reset to the Controller
16 Reset Mechanisms
The Controller may be reset, completely or partially, through the following mechanisms:
Primary reset using the PCI reset signal PCIRST#
Power State reset resulting from the transition of the Modem Function (Function 1) from D3 to D0 power state
Docking reset resulting from change in docking state
Codec Warm Reset
The effect of a primary reset can be modified through the following:
Input signal GATE_RST#
Internal gating of PCIRST#
16.1
Primary Reset (PCIRST#)
Assertion of the PCIRST# signal causes the entire Controller device to be asynchronously forced into the reset state.
Deassertion of PCIRST# then initiates internal reset processing, terminating with the start of normal operation.
The PME_en and PME_status bits of the PCI configuration space are reset to zero by the primary reset (PRIRST#), when not
disabled by GATE_RST#.
Reset signals generated by the Controller (MRESET#, RESET#, RESETD#) are all asserted during this primary reset
process.
The primary reset (PCIRST#) may be disabled by asserting GATE_RST#.
The primary reset may also be disabled internally by the on-chip controller to allow selected logic to continue operating in the
D3cold state. The PCI Configuration Space of all of these functions will always be reset by the PCIRST# signal, regardless of
GATE_RST#.
16.2
Power State Reset
When any of the three functions are programmed from the D3 power state to the D0 power state, the PCI configuration space
for that function is reset to the uninitialized state. Only the PCI configuration space is affected. The device will not respond to
PCI accesses during the re-load procedure.
16.3
Software Reset
A software reset may be initiated which will be identical to a Primary Reset, except that the PCI Configuration space will be
unaffected. This reset cannot be blocked by the GATE_RST#.
16.4
Docking Reset
A change in the PC docking status (as indicated by the DOCKSENSE input) will cause a Docking Reset to be initiated. This
reset is similar to a Primary Reset, except that the PCI interfaces and the Modem Function (Function 1) will be unaffected.
The Audio Function (Function 0) and the Joystick Function (Function 2) will be affected. When this reset is complete, the
Controller will be using the newly selected Primary or Secondary (docking station) Codec. Since most of the Audio
functionality is reset by this, the Controller’s internal functions 0 and 2 will be unavailable during the reset sequence.
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