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| 型号： | DSRT-L030-011 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, XMA |
| 文件页数： | 62/86页 |
| 文件大小： | 667K |
| 代理商： | DSRT-L030-011 |
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RipTide PCI Audio/Comm Device Family Product Description
1167
ROCKWELL PROPRIETARY INFORMATION
65
13.2.1
VIO and the D3cold State
Controller ESD protection design requires that certain precautions be taken to avoid excessive current draw through the VDD
pins. If the VDD voltage level, or the level on any input, is greater than the VIO voltage level, internal diodes will become
forward biased, resulting in current flow from VDD, or the signal pin, to VIO which will cause permanent damage to the
Controller. To avoid this in +3.3V VDD PCI systems, VIO should be connected to the same supply source as are the VDD
pins. In a +5V VIO PCI system, VIO must be attached to a +5V supply. In either case, the voltage level on the VIO pin
must never fall below the VDD voltage level.
13.2.2
PME Generation
The Controller can assert the PCI PME# signal based on certain events. Only the Modem Function (function 1) is capable of
generating PME#. There are three mechanisms by which function 1 is caused to initiate PME. A power management event
(PME#) may be asserted due to any GPIO event whether the GPIO was triggered at the Controller pins or the Codec GPIO
pins.
To use any of the PME# generation mechanisms, the host must first program the PME_En bit in the Power Management
CSR.
13.2.3
Connection to PCI PME# Signal
The PCI Power Management Specification requires that ‘When power is removed from its PME# generation logic, the
unpowered output does not present a low impedance path to ground or any other voltage”. Two situations exist. The first, the
Controller will retain its power supply whenever the remainder of the system is active. The second, the Controller may lose
power independently of the rest of the system, thus the output driver would form a low impedance path to ground, which is not
allowed.
Although the Controller can drive the PME# signal, it must not, however, affect the PME# system signal when power is not
available to the Controller. An external circuit must be provided to isolate the Modem DMA/Interface Controller PME# signal
from the system PME# signal. A FET may be used such that when it is turned OFF, it isolates the modem DMA interface
controller PME# signal from the system PME# signal.
To accommodate this, the PME# output can be configured to supply an active-high, always driven output, which can be used
to drive the gate of an N-type isolation FET (external to the controller as shown in the latest Reference schematics). In this
configuration, the unpowered controller would simply pull the gate of the N-FET low, which would not affect the system PME#
signal. The following schematic illustrates in simple terms, the recommended usage of the Controller in systems where power
may be lost to the Controller independently of the rest of the system. At power-on reset, the PME# pin will default to the open-
drain configuration. This will result in the PME# pin to float and potentially cause the System PME# to be asserted until the
pin is configured as an active-high output. The pull-down resistor is used to prevent system PME# assertion during this time.
PME# Pin
System PME#
GND
Controller
13.2.4
Warm Reset PME Assertion
The AC-Link interface module will cause PME# to be asserted upon detecting a low to high transition on the SDATA_IN pin.
This allows the codec to wake the host computer system upon detection of an appropriate event, such as a telephone ring.
Caller ID in D3 Cold state is supported in this manner. If Vaux is not detected, no Caller ID in D3 Cold state is supported.
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