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参数资料
| 型号： | DSRT-L030-011 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, XMA |
| 文件页数： | 8/86页 |
| 文件大小： | 667K |
| 代理商： | DSRT-L030-011 |
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RipTide PCI Audio/Comm Device Family Product Description
16
ROCKWELL PROPRIETARY INFORMATION
1167
4.2
ACC Pin Signal Descriptions
4.2.1
PCI Bus Interface
Signal
Type
Level
I
OL/IOH
Reset
State
Std.
Load
Description
AD[31:0]
Ip/Opts
PCI
Z
PCI
Multiplexed Address and Data. Address inputs and Data
input/outputs are multiplexed on the AD[31:0] pins.
CBE#[3:0]
Ip/Opts
PCI
Z
PCI
Bus Command and Bus Enable. Bus Command and Byte Enables
are multiplexed on the CBE#[3:0] pins. During the address phase of
a transaction, CBE[3:0]# define the Bus Command. During the data
phase, CBE[3:0]# are used as Byte Enables.
FRAME#
Ip/Opsts
PCI
Z
PCI
Cycle Frame. FRAME# is driven by the current master to indicate
the beginning and duration of an access.
IRDY#
Ip/Opsts
PCI
Z
PCI
Initiator Ready. IRDY# is used to indicate the initiating agent’s (bus
master’s) ability to complete the current data phase of the
transaction. IRDY# is used in conjunction with TRDY#.
TRDY#
Ip/Opsts
PCI
Z
PCI
Target Ready. TRDY# is used to indicate the Bus Interface’s ability
to complete the current data phase of the transaction. TRDY# is
used in conjunction with IRDY#.
PAR
Ip/Opts
PCI
Z
PCI
Parity. Parity is even parity across AD[31:0] and CBE[3:0]#. The
master drives PAR for address and write data phases; the Bus
Interface drives PAR for read data phases.
STOP#
Ip/Opsts
PCI
Z
PCI
Stop. STOP# is asserted to indicate the Bus Interface is requesting
the master to stop the current transaction.
DEVSEL#
Ip/Opsts
PCI
Z
PCI
Device Select. When actively driven, DEVSEL# indicates the
driving device has decoded its address as the target of the current
access. As an input, DEVSEL# indicates whether any device on the
bus has been selected.
IDSEL
Ip
PCI
Initialization Device. IDSEL input is used as a chip select during
configuration read and write transactions.
PERR#
Ip/Opsts
PCI
Z
PCI
Parity Error. PERR# is used for the reporting of data parity errors.
SERR#
Opod
PCI
Z
PCI
System Error. SERR# is an open drain output asserted to report
address parity errors, data parity errors on the Special Cycle
command, or any other system error where the result will be
catastrophic.
REQ#
Opts
PCI
H
PCI
Request. REQ# is used to indicate to the arbiter that this agent
desires use of the bus.
GNT#
Ipts
PCI
Grant. GNT# is used to indicate to the agent that access to the bus
has been granted.
PCICLK
Ip
PCI
PCI Bus Clock. The PCICLK input provides timing for all
transactions on the PCI Bus.
PCIRST#
Ip
PCI
PCI Bus Reset. Active low input asserted to initialize PCI-specific
registers, sequencers, and signals to a consistent reset state.
INTA#
Opod
PCI
Z
PCI
Interrupt A. INTA# is an open drain output asserted to request
interrupt servicing.
INTB#
Opod
PCI
Z
PCI
Interrupt B. INTB# is an open drain output asserted to request
interrupt servicing.
CLKRUN
Ip/Opod
PCI
Z
PCI
Clock Running for CardBus. CLKRUN# is an input used to
determine the status of CLK and an open drain output used to
request starting or speeding up CLK. Connect to GND through 1K
for PCI designs.
PME#
Opod
PCI
Z
PCI
Power Management Enable. Active low output asserted when
RINGWAKE# input is asserted. This signal should be used only if
the target PCI Bus supports power management wake-up event.
This signal should be connected to a circuit that controls the PCI
Bus PME# signal. When PME# is asserted, the PCI PME# signal
should be pulled low, otherwise it should float.
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