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| 型号： | DSRT-L030-011 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, XMA |
| 文件页数： | 55/86页 |
| 文件大小： | 667K |
| 代理商： | DSRT-L030-011 |
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RipTide PCI Audio/Comm Device Family Product Description
1167
ROCKWELL PROPRIETARY INFORMATION
59
8
AC-link Interface Description
The Controller implements an AC’97 compatible AC-link serial interface for connection with AMC’97 compliant combined
audio/modem codec devices. AC-link is a 5-pin digital serial interface which allows for time multiplexed transfer of command
data/status and audio/modem stream sample data to and from the AMC’97 codec. The link is tied to a 48 kHz sample period.
The controller does not support the ‘double rate’ AC-Link feature, and therefore is limited to streams operating at or below
48KHz.
For more detailed information on the AC-link Interface, refer to the RipTide Codec Product Description.
Table 21. AC-link Interface Signals
Name
I/O
Description
BIT_CLK
I
12.288MHz Serial Bit Clock
SYNC
O
48 kHz Sample Period Synchronization
SDATA_OUT
O
Serial Data Out
SDATA_IN
I
Serial Data In
RESET#
O
Codec Reset.
8.1
AC-link Protocol
The BIT_CLK is driven by the Codec at 12.288 MHz. There are therefore 256 cycles of BIT_CLK in a 48 kHz sample period.
Transitions on the SYNC and SDATA_IN/SDATA_OUT signals occur coincidentally with the rising edges of BIT_CLK. These
signals should be sampled by their receiver on the next falling edge of BIT_CLK.
SYNC is driven by the Controller with a 48 kHz period. The waveform is high for 16 BIT_CLK cycles and low for the remaining
240 cycles.
An AC-link frame is defined to begin one clock period after the rising edge of SYNC. (i.e., at the rising edge of BIT_CLK
following the one at which SYNC transitioned from 0 to 1) The frame is divided into 13 slots, numbered 0 through 12, in the
order in which they are transmitted (12 is last). The first slot (0) is 16 BIT_CLK cycles long. The remaining 12 slots are each
20 BIT_CLK cycles long. The bit cycles within each slot are numbered from 15 to 0 (slot 0) or 19 to 0 (slots 1 through 12),
again in the order in which they are transmitted (0 is last).
1166FX AC-LINK
AC '97
Digital Controller
AMC '97
Codec
SYNC
BIT_CLK
SDATA_OUT
SDATA-IN
RESET#
Figure 10. AC-link Interface
8.2
Cold Reset
At power-up, the RESET# signal, which provides reset to the AMC’97 codec, is held low for the appropriate amount of time
and then deasserted. Other portions of the controller will remain reset until the BIT_CLK signal has had enough time to
become active and the controller’s internal logic has had enough time to stabilize.
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