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| 型号： | DSRT-L030-011 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, XMA |
| 文件页数： | 46/86页 |
| 文件大小： | 667K |
| 代理商： | DSRT-L030-011 |
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RipTide PCI Audio/Comm Device Family Product Description
50
ROCKWELL PROPRIETARY INFORMATION
1167
7.1.1.4
Status
The status register monitors the progress of PCI events within the Controller. Status bits can be read and they can be
cleared, but they cannot be set. Status bits are cleared by writing a 1 to that bit position. Writing a 0 to a status bit has no
affect. The status register bits are defined as follows:
Status Register Bits
Bit
R/W/C
Default
Description
3-0
r
0
Reserved.
4r
1
Capabilities List. Indicates that an extended capabilities list exists and is pointed to by the Cap_Ptr field at
configuration offset 0x34. All 3 functions include a power management capabilities list. Read Only.
5r
0
66 MHz Capable. Not supported.
6r
0
UDF Supported. Not supported.
7r
0
Fast Back-To-Back Capable. Not supported.
8r/c
0
Data Parity Reporting. This bit is only implemented by bus masters. It is set when three conditions are met:
1) the bus agent asserted PERR# itself or observed PERR# asserted; 2) the agent setting the bit acted as the
bus master for the operation in which the error occurred; and 3) the Parity Error Response bit (Command
Register) is set.
10-9
r
01
Device Select Timing. These bits encode the timing of DEVSEL#. These are encoded as 00 for fast, 01 for
medium, and 10 for slow (11 is reserved.) These bits are read-only and must indicate the slowest time that a
device asserts DEVSEL# for any bus command except Configuration Read and Configuration Write.
11
r
0
Signaled Target Abort. Not supported.
12
r/c
0
Received Target Abort. This bit must be set by a master device whenever its transaction is terminated with
Target-Abort. All master devices must implement this bit.
13
r/c
0
Received Master Abort. This bit must be set by a master device whenever its transaction (except for Special
Cycle) is terminated with Master-Abort. All master devices must implement this bit.
14
r/c
0
Signaled System Error. This bit must be set whenever the device asserts SERR#. Devices who will never
assert SERR# do not need to implement this bit.
15
r/c
0
Detected Parity Error. This bit must be set by the device whenever it detects a parity error, even if parity
error handling is disabled (as controlled by bit 6 in the Command register).
7.1.1.5
Revision ID
Revision ID is an 8-bit field that specifies a device specific revision identifier. This value is chosen by Rockwell (vendor); (zero
is acceptable. This field should be viewed as a Rockwell (vendor) defined extension to the Device ID. This register is also
readable by the Controller. The default value for the Revision ID is 03.
7.1.1.6
Class Code
Class Code is a 24-bit field with three 8 bit sub-fields. The upper byte is a base class code. The middle byte is a sub-class
code. The lower byte specifies any register-level programming interface that may exist.
For the Audio logical device: Class Code = 040100
Base Class Code: 04 = multimedia device
Sub Class Code: 01 = audio device
Prog I/F: 00 = none
For the Modem logical device: Class Code = 078000
Base Class Code: 07 = simple communications controller
Sub Class Code: 80 = “other”
Prog I/F: 00 = none
For the Joystick logical device: Class Code = 098000
Base Class Code: 09 = input device
Sub Class Code: 80 = “other”
Prog I/F: 00 = none
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