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| 型号： | DSRT-L030-011 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, XMA |
| 文件页数： | 66/86页 |
| 文件大小： | 667K |
| 代理商： | DSRT-L030-011 |
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RipTide PCI Audio/Comm Device Family Product Description
1167
ROCKWELL PROPRIETARY INFORMATION
69
18 Design Layout Guidelines for 2-Layer PCI Board
Purpose of this section is to provide design guidelines for layout of PCI boards utilizing only two layers.
18.1
General Guidelines
1.
Tie separate ground planes together at only one point.
2.
Fill bare board areas (top and bottom) with ground or Vcc (use 50-50 ratio or favor ground).
3.
Provide 15 to 40 mil spacing between analog and digital ground traces.
4.
Provide 25 mil minimum width for power and ground traces.
5.
Provide 15 mil minimum width for crystal traces.
6.
Avoid inconsistencies in routing; EMI radiation will occur every time a trace changes it’s impedance.
7.
Prevent turns greater than 45 degrees.
8.
Prevent different thickness on a trace.
9.
Apply ground fill under crystals.
10. Follow the examples illustrated in Section 18.2.
18.1.1
Placement of RipTide Devices
1.
Rotate and position the RipTide devices to minimize the number of vias on all traces.
2.
Rotate and position the Controller to minimize trace lengths of PCI signals.
3.
Rotate and position the Codec so the Analog section is kept away from PCI area and other fast signals.
18.1.2
Trace Routing and Length on PCI Signals
1.
The RipTide devices pinouts are arranged such that signal routing to the PCI connector can be done with at most one
via. If any signals cross, the net-list is wrong. The essential rules are: consistent trace aperture, minimum number of vias,
trace bends at 45 degree angle maximum.
2.
Provide 15 mils minimum trace widths for the PCICLK, MRXCLK, MTXCLK, MPLLOUT, BIT_CLK clock signals. Keep the
trace widths as consistent as possible to minimize impedance changes. This also means that the trace going into a
series terminating resistor should the same on both sides. No vias are permitted on the clock-carrying traces. Clocks
should always be routed on one side of the board.
3.
PCI 2.1 specification puts a strict length limit on PCI signals. The PCICLK trace must be 2.5
± 0.1" in length; other PCI
signal traces should be less than 1.5" in length. Rockwell reference designs achieve the required length by performing a
zigzag routing with (a) rounded corners for lower EMI and (b) approximately double width traces compared to other PCI
interface signals for lower impedance/EMI.
4.
The PCICLK signal is one of the largest sources of EMI on PCI peripheral designs. Surround this trace on both sides by
guard-bands of digital ground that envelope PCICLK along the entire length. This technique also aims at approximating
the required impedance relationship of PCICLK with respect to ground distribution. Connect this guard-band to ground
pins immediately next to the PCICLK pin at the PCI connector. See Section 18.2.
5.
Provide guard-bands also for the MRXCLK, MTXCLK, MPLLOUT, BIT_CLK clock traces. Decouple guard-bands with a
surface mount capacitors.
18.1.3
Grounding
Because EMI always takes the easiest path to earth ground, ensure that EMI has no problem finding it in a harmless way.
1.
Provide ground paths to the bracket. The best ground is provided by the bracket, not by the ground pins on the bus
(while the ground pins provide effective signal returns to the motherboard, at high frequencies these traces become
inductors that acquire higher impedance with increasing frequency). The bracket ground which connects to the chassis is
quite beneficial in dealing with unwanted EMI. This includes using both bracket screws with as much contact surface
area as possible to ground (including under the screw head), and pin 1 on the audio connectors (which tie to the bracket
via the connector chassis and screw). On the bracket edge of the board, place a ground strip on both sides of the board.
The bracket ground (chassis ground) depends on the PC’s case, so choose a system for FCC testing with good EMI
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