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| 型号： | DSRT-L030-011 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, XMA |
| 文件页数： | 44/86页 |
| 文件大小： | 667K |
| 代理商： | DSRT-L030-011 |
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RipTide PCI Audio/Comm Device Family Product Description
1167
ROCKWELL PROPRIETARY INFORMATION
49
7.1.1
PCI Configuration Space Field Definitions
7.1.1.1
Vendor ID
Vendor ID is a 16-bit read-only field identifying the device manufacturer. The power-on default value for the Rockwell RipTide
Vendor ID is 0x127A for all three functions, and can be overwritten by the use of an external serial EEPROM after reset
events.
7.1.1.2
Device ID
Device ID is a 16-bit read-only field that identifies the particular device. This field defaults to the 0x4300, 0x4301, 0x4302
addresses for the Audio, Modem and Joystick devices, respectively. This identifier is allocated by the vendor. The power-on
default value can be overwritten by the use of an external serial EEPROM after reset events.
7.1.1.3
Command
The command register controls the basic PCI capabilities. The command register bits are defined as follows:
Command Register Bits
Bit
R/W/C
Default
Description
0r/w
1
I/O Access Enable. Controls a device’s response to I/O Space accesses. A value of 0 disables the device
response. A value of 1 allows the device to respond to I/O Space accesses.
1r/w
1
Memory Access Enable. Controls a device’s response to Memory Space accesses. A value of 0 disables
the device response. A value of 1 allows the device to respond to Memory Space accesses.
2r/w
1
Master Enable. Controls a device’s ability to act as a master on the PCI Bus. A value of 0 disables the device
from generating PCI accesses. A value of 1 allows the device to behave as a bus master.
3r
0
Special Cycle Recognition. Not supported.
4r
0
Memory Write and Invalidate Enable. Not supported.
5r
0
VGA Palette Snoop Enable. Not supported.
6r/w
na
Parity Error Response. This bit controls the device’s response to parity errors. When the bit is set, the
device must take its normal action when a parity error is detected. When the bit is 0, the device must ignore
any parity errors that it detects and continue normal operation.
7r
0
Wait Cycle Enable. Not supported.
8r/w
0
System Error Enable. This bit is an enable bit for the SERR# driver. A value of 0 disables the SERR# driver.
A value of 1 enables the SERR# driver.
9r
0
Fast Back-to-Back Enable. Not supported.
10-15
na
Reserved.
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