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参数资料
| 型号： | DSRT-L030-011 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, XMA |
| 文件页数： | 57/86页 |
| 文件大小： | 667K |
| 代理商： | DSRT-L030-011 |
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RipTide PCI Audio/Comm Device Family Product Description
60
ROCKWELL PROPRIETARY INFORMATION
1167
8.3
Warm Reset
An AMC’97 Warm Reset is supported by the controller. The sequence of events involved in placing the codec into its low
power state and waking it up again are:
Controller causes PR4 bit to be set in the codec sending appropriate address/data in slots 1 and 2.
AC-Link interface detects that PR4 has been set.
AC-Link interface sends frame to codec containing PR4 bit, but no valid data slots. DATA_OUT is held low from this point
on.
AC-Link interface pauses for 4 frame times (ensuring specified delay prior to assertion of warm reset)
AC-Link interface monitors SDATA_IN for positive transition.
PCI bus may or may not enter B3 state.
AC-Link interface waits for one of three possible triggering events:
Low to high transition on SDATA_IN
Trailing edge of PCI reset
Host writes D0 to any of the three configuration space Power State registers
If a transition on SDATA_IN was the triggering event, the AC-Link interface causes PME to be asserted through PCI
function 1
AC-Link interface asserts SYNC for approximately 1uS
AC-Link interface pauses for 100uS
AC-Link interface sets interrupts to the on-chip processor.
9
I
2S Interface Description
The Controller supports two I
2S interfaces to allow direct connection to digital audio sources with this style of interface. Each
three-line serial bus consists of a time-multiplexed serial data input (SDx or I2SxDATA), a word select input (WSx or
I2SxFRM) and a bit clock input (SCKx or I2SxCLK). The Controller I
2S ports operate as bus slaves, i.e., the bit clock and word
select are provided by an external source. The master is the I
2S source and the slave is the Controller I2S interface.
The interface accepts input data at sample rates up to 50 kHz. There is effectively no lower limit on the incoming data rate
except that it may be impractical for the sample-rate tracker to function on very slow streams. The interface assumes that the
data source is operating asynchronously to the Controller.
Table 22. I
2S Interface Signal Definitions
Signal Name
I/O
Description
I2S0CLK
I
Serial Clock In 0 (SCK0)
I2S0FRM
I
Serial Word Select 0 (WS0)
I2S0DATA
I
Serial Data In 0 (SD0)
I2S1CLK
I
Serial Clock In 1 (SCK1)
I2S1FRM
I
Serial Word Select 1 (WS1)
I2S1DATA
I
Serial Data In 1 (SD1)
9.1
Serial Input Data Format
If sample data coming into the unit over the serial bus is less than 16 bits in length, it is left justified, with zeros filled into the
missing least significant bit positions. If sample data coming into the unit is more than 16 bits in length, it is also left justified,
with the extra least significant bits truncated. Serial data is transmitted in two’s complement with the MSB first. The MSB is
transmitted first because the transmitter (master’s external audio source) and receiver (Controller’s I
2S port) may have
different word lengths. It isn’t necessary for the transmitter to know how many bits the receiver can handle, nor does the
receiver need to know how many bits are being transmitted.
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