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参数资料
| 型号： | PC87393F-VJG |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | 100-Pin LPC SuperI/O Devices for Portable Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 119/148页 |
| 文件大小： | 1733K |
| 代理商： | PC87393F-VJG |
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3.0
General-Purpose Input/Output (GPIO) Port
Note: This section applies to the PC87392, PC87393 and PC87393F only.
This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations.
For the device specific implementation, see the
3.1
OVERVIEW
The GPIO port is an 8-bit port, which is based on eight pins. It features:
q
Software capability to manipulate and read pin levels
q
Controllable system notication by several means based on the pin level or level transition
q
Ability to capture and manipulate events and their associated status
q
Back-drive protected pins.
GPIO port operation is associated with two sets of registers:
q
Pin Conguration registers, mapped in the Device Conguration space. These registers are used to statically set up
the logical behavior of each pin. There are two 8-bit register for each GPIO pin.
q
Four 8-bit runtime registers: GPIO Data Out (GPDO), GPIO Data In (GPDI), GPIO Event Enable (GPEVEN) and
GPIO Event Status (GPEVST). These registers are mapped in the GPIO device IO space (which is determined by
the base address registers in the GPIO Device Conguration). They are used to manipulate and/or read the pin val-
ues, and to control and handle system notication. Each runtime register corresponds to the 8-pin port, such that bit
n in each one of the four registers is associated with GPIOXn pin, where X is the port number.
Each GPIO pin is associated with ten configuration bits and the corresponding bit slice of the four runtime registers, as
shown in Figure 8.
The functionality of the GPIO port is divided into basic functionality that includes the manipulation and reading of the GPIO
pins, and enhanced functionality. The basic functionality is described in Section 3.2. The enhanced functionality which in-
cludes the event detection and system notification is described in Section 3.3.
Figure 8. GPIO Port Architecture
GPIO Pin
Select (GPSEL)
Conguration (GPCFG)
GPDOX
GPDIX
GPEVENX
GPEVSTX
Runtime
Registers
GPIOX Base Address
Event
Bit n
Port and Pin
8 GPCFG
Registers
x8
GPIOXn
Pin
x8
GPIOXn CNFG
Interrupt
x8
GPIOXn
Port Logic
X = port number
n = pin number, 0 to 7
Pending
Indicator
Request
SMI
GPIO Pin Event
Routing (GPEVR)
8 GPEVR
Registers
GPIOXn ROUTE
Select
Event
Routing
Control
Register
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PC87393VJG | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:IC, SUPER I/O DEVICE, TQFP-100, Logic Device Type:Buffer, Supply Voltage Min:3V, |
| PC87393-VJG | 制造商:NSC 制造商全称:National Semiconductor 功能描述:100-Pin LPC SuperI/O Devices for Portable Applications |
| PC87410 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PC87410 PCI-IDE Interface Controller |
| PC87410VLK | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87413 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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