参数资料
型号: PC87393F-VJG
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 外设及接口
英文描述: 100-Pin LPC SuperI/O Devices for Portable Applications
中文描述: MULTIFUNCTION PERIPHERAL, PQFP100
封装: TQFP-100
文件页数: 9/148页
文件大小: 1733K
代理商: PC87393F-VJG
106
www.national.com
7.0
X-Bus Extension
Notes: This section applies to the PC87393 and PC87393F only.
FWH-related descriptions apply to the PC87393F only.
7.1
OVERVIEW
The PC8739x provides an X-Bus extension to the LPC bus to enable the ISA-like interface to external 8-bit peripherals. De-
code logic, described in the
Device Architecture and Configuration chapter, defines the addresses for which the X-Bus gen-
erates transactions. These transactions may be in the I/O address space and the memory address space or in the FWH
memory address space. Using the X-Bus interface, the PC8739x serves as a bridge for such transactions into the X-Bus.
Figure 21 is a schematics block diagram of the X-Bus bridging function. For details on the decoder functions, see the
Device
Architecture and Configuration chapter. All other functions are described in detail in this chapter.
Figure 21. X-Bus Block Diagram
7.2
IRQ ROUTING
The PC8739x supports up to four IRQ inputs, PIRQA through PIRQD. These pins may be used to support legacy devices
that are connected on the X-Bus. The PC8739x enables any of these interrupts to be routed to any one of fifteen host IRQs.
The IRQ inputs are mapped by X-Bus PIRQA-D Mapping registers at F8h and F9h. XIRQCA through XIRQCD registers en-
able the user to define the interrupt as active high or low, and to route it to a wake-up event.
7.3
X-BUS TRANSACTIONS
The X-Bus extension supports 8-bit I/O or memory read/write cycles.
The zone mapping of the chip select signals determines how X-Bus read and write cycles correspond to memory and I/O
bus cycles. The zone mapping to a select signal, XCS1-0, must be enabled regardless of whether the I/O device is using
the chip select signal. Signal mapping to a pin may be disabled when the select signal is not required for an off-chip interface.
LPC
Bus
LPC
Interface
Internal
Bus
X-Bus
Configuration
I/O
Address
Memory
Address
Decoder
Bus
Cycle
Generator
MUX
XCS0
XCS1
XA19-0
X-Bus Interface
Device Architecture Component
XRD XWR
XSTB2-0
XRDY
XD7-0
IRQ Router
IRQ
Serializer
PIRQ(A-D)
XCNF2-0
XIORD XIOWR
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