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参数资料
| 型号： | PC87393F-VJG |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | 100-Pin LPC SuperI/O Devices for Portable Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 122/148页 |
| 文件大小： | 1733K |
| 代理商： | PC87393F-VJG |
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3.0 General-Purpose Input/Output (GPIO) Port (Continued)
75
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Figure 11. GPIO Event Routing Mechanism
The GPEVST register is a general-purpose edge detector which may be used to reflect the event source pending status for
edge-triggered events.
The term
active edge refers to a change in a GPIO pin level that matches the Event Polarity bit (1 for rising edge and 0 for
falling edge).
Active level refers to the GPIO pin level that matches the Event Polarity bit (1 for high level and 0 for low level).
The corresponding bit of the GPEVST register is set by hardware whenever an active edge is detected, regardless of any
other bit settings. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored.
A GPIO pin is in event pending state if the corresponding bit of the GPEVEN register is set and either:
q
The Event Type is level and the pin is in active level, or
q
The Event Type is edge and the corresponding bit of the GPEVST register is set.
The target means of system notification is asserted if at least one GPIO pin is in event pending state.
The selection of the target means of system notification is determined by the GPEVR register. If IRQ is selected as one of the
means for the system notification, the specific IRQ line is determined by the IRQ selection procedure of the device configura-
tion. The assertion of any means of system notification is blocked when the GPIO functional block is deactivated.
If the output of a GPIO pin is enabled, it may be put in event pending state by the software when writing to the GPDO register.
An pending edge event may be cleared by clearing the corresponding GPEVST bit. However, a level event source may not
be released by software (except for disabling the source), as long as the pin is in active level. When level event is used, it
is recommended to disable the input debouncer.
Upon de-activation of the GPIO port, the GPEVST register is cleared and access to both the GPEVST and GPEVEN regis-
ters is disabled. All system notification means including the target IRQ line are detached from the GPIO and de-asserted.
Before enabling any system notification, it is recommended to set the desired event configuration, and then verify that the
status registers are cleared.
3.4
GPIO PORT REGISTERS
The register maps in this chapter use the following abbreviations for Type:
q
R/W = Read/Write
q
R = Read from a specic address returns the value of a specic register. Write to the same address is to a different
register.
q
W=Write
q
RO = Read Only
q
R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
Event Pending Indicator
SMI
IRQ
Event
Routing
Logic
Enable
IRQ
GPIO Pin Event Routing Register
Bit 1
Bit 0
Routed Events
from other GPIO Pins
Routing
Enable
SMI
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相关代理商/技术参数 |
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| PC87393VJG | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:IC, SUPER I/O DEVICE, TQFP-100, Logic Device Type:Buffer, Supply Voltage Min:3V, |
| PC87393-VJG | 制造商:NSC 制造商全称:National Semiconductor 功能描述:100-Pin LPC SuperI/O Devices for Portable Applications |
| PC87410 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PC87410 PCI-IDE Interface Controller |
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