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参数资料
型号： PC87393F-VJG
厂商： NATIONAL SEMICONDUCTOR CORP
元件分类： 外设及接口
英文描述： 100-Pin LPC SuperI/O Devices for Portable Applications
中文描述： MULTIFUNCTION PERIPHERAL, PQFP100
封装： TQFP-100
文件页数： 56/148页
文件大小： 1733K
代理商： PC87393F-VJG
1.0 Signal/Pin Connection and Description (Continued)
15
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1.2
BUFFER TYPES AND SIGNAL/PIN DIRECTORY
The signal DC characteristics are denoted by a buffer type symbol, described briefly below and in further detail in Section
9.2. The pin multiplexing information refers to three different types of multiplexing:
q
Multiplexed, denoted by a slash (/) between pins in the diagram in Section 1.1. Pins are shared between two different
functions. Each function is associated with different board connectivity, and normally, the function selection is deter-
mined by the board design and cannot be changed dynamically. The multiplexing options must be congured by the
BIOS upon power-up, in order to comply with the board implementation.
q
Multiple Mode, denoted by an underscore (_) between pins in the diagram in Section 1.1. Pins have two or more
modes of operation within the same function. These modes are associated with the same external (board) connectiv-
ity. Mode selection may be controlled by the device driver, through the registers of the functional block, and do not
require a special BIOS setup upon power-up. These pins are not considered multiplexed pins from the SuperI/O con-
guration perspective. The mode selection method (registers and bits) as well as the signal specication in each
mode, are described within the functional description of the relevant functional block.
q
Parallel Port Multiplexer, denoted by a slash (/) between pins in the diagram in Section 1.1. Parallel Port pins can be
used to support external Floppy Disk Controller signals when the PPM is enabled and bit 7 of the SuperI/O Congu-
ration 5 register (SIOCF5) is cleared. See Table 3 for a summary of all PPM options.
1.3
PIN MULTIPLEXING
Table 2 groups all multiplexed PC8739x pins in their associated functional blocks, and provides links to the relevant config-
uration registers and bit values for selecting multiplexed options.
Table 2. Pin Multiplexing Conguration
Table 1. Buffer Types
Symbol
Description
INC
Input, CMOS compatible
INPCI
Input, PCI 3.3V
INSTRP
Input, Strap pin with weak pull-down during strap time
INT
Input, TTL compatible
INTS
Input, TTL compatible with Schmidt Trigger
OPCI
Output, PCI 3.3V
Op/n
Output, push-pull buffer that is capable of sourcing
p mA and sinking n mA
ODn
Output, open-drain output buffer that is capable of sinking
n mA
PWR
Power pin
GND
Ground pin
Functional
Block
Signal
Functional
Block
Signal
Functional
Block
Signal
Functional
Block
Signal
Cong
Section
GPIO
GPIO00
X-Bus
XD0
Game Port
JOYABTN1
2.10.3
GPIO
GPIO01
X-Bus
XD1
Game Port
JOYBBTN1
2.10.3
GPIO
GPIO02
X-Bus
XD2
Game Port
JOYAY
2.10.3
GPIO
GPIO03
X-Bus
XD3
Game Port
JOYBY
2.10.3
GPIO
GPIO04
X-Bus
XD4
Game Port
JOYBX
2.10.3
GPIO
GPIO05
X-Bus
XD5
Game Port
JOYAX
2.10.3
GPIO
GPIO06
X-Bus
XD6
Game Port
JOYBBTN0
2.10.3
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PC87393VJG 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:IC, SUPER I/O DEVICE, TQFP-100, Logic Device Type:Buffer, Supply Voltage Min:3V,
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