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参数资料
| 型号： | PC87393F-VJG |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | 100-Pin LPC SuperI/O Devices for Portable Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 120/148页 |
| 文件大小： | 1733K |
| 代理商： | PC87393F-VJG |
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3.0 General-Purpose Input/Output (GPIO) Port (Continued)
73
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3.2
BASIC FUNCTIONALITY
The basic functionality of each GPIO pin is based on four configuration bits and a bit slice of runtime registers GPDO and
GPDI. The configuration and operation of a single pin GPIOXn (pin n in port X) is shown in Figure 9.
Figure 9. GPIO Basic Functionality
3.2.1
Configuration Options
The GPCFG register controls the following basic configuration options:
Port Direction - Controlled by the Output Enable bit (bit 0)
Output Type - Push-pull vs. open-drain. It is controlled by Output Buffer Type (bit 1) by enabling/disabling the pull-up
portion of the output buffer.
Weak Static Pull-Up - May be added to any type of port (input, open-drain or push-pull). It is controlled by Pull-Up Control
(bit 2).
Pin Lock - GPIO pin may be locked to prevent any changes in the output value and/or the output characteristics. The
lock is controlled by Lock (bit 3). It disables writes to the GPDO register bits, and to bits 0-3 of the GPCFG register (In-
cluding the Lock bit itself). Once locked, it can be released by hardware reset only.
3.2.2
Operation
The value that is written to the GPDO register is driven to the pin, if the output is enabled. Reading from the GPDO register
returns its contents, regardless of the pin value or the port configuration. The GPDI register is a read-only register. Reading
from the GPDI register returns the pin value, regardless of what is driving it (the port itself, configured as an output port, or
the external device when the port is configured as an input port). Writing to this register is ignored.
Activation of the GPIO port is controlled by external device specific configuration bit (or a combination of bits). When the port
is inactive, access to GPDI and GPDO registers is disabled, and the inputs are blocked. However, there is no change in the
port configuration and in the GPDO value, and hence there is no effect on the outputs of the pins.
GPIO Device
Pin
Data Out
Data In
Enable
Output
Enable
Output
Internal
Bus
Lock
Type
Static
Pull-Up
Enable
GPIO Pin Conguration (GPCFG) Register
Push-Pull =1
Pull-Up
Control
Read Only
Read/Write
Bit 3
Bit 2
Bit 1
Bit 0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PC87393VJG | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:IC, SUPER I/O DEVICE, TQFP-100, Logic Device Type:Buffer, Supply Voltage Min:3V, |
| PC87393-VJG | 制造商:NSC 制造商全称:National Semiconductor 功能描述:100-Pin LPC SuperI/O Devices for Portable Applications |
| PC87410 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PC87410 PCI-IDE Interface Controller |
| PC87410VLK | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87413 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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