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| 型号： | PC87393F-VJG |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | 100-Pin LPC SuperI/O Devices for Portable Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 3/148页 |
| 文件大小： | 1733K |
| 代理商： | PC87393F-VJG |
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6.0 Musical Instrument Digital Interface (MIDI) Port (Continued)
100
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The values of these bits are set by the MIDI Port hardware and are not affected by reading the MSTAT register.
The following status indications are provided by the MIDI Port, although they are not included in the Legacy definition of the
MIDI Port:
q
Receive FIFO Full
q
Transmit FIFO Empty
q
Receive Overrun Error
q
MIDI Port Operation Mode
The Receive FIFO Full and Transmit FIFO Empty status flags are reflected by MSTAT register bits 5 and 2, respectively.
These bits are updated only when the MIDI Port operates in UART mode or when in Pass-Thru mode with the Receive FIFO
enabled. Otherwise, these bits are constantly cleared. The values of these bits are set by the MIDI Port hardware and are
not affected by reading the MSTAT register.
The Receive Overrun Error flag indicates that serial data has been received by the MIDI Communication Engine while the
Receive Buffer of FIFO was full. This flag is reflected by bit 3 of the MSTAT register. It is updated in both Pass-Thru and
UART modes. When a Receive Overrun Event occurs, the data in the Receive Buffer/FIFO is kept and all incoming data is
lost. Incoming data will keep getting lost until there is room in the Receive Buffer/FIFO to accept it. The Receive Overrun
Error status flag is cleared when the MSTAT register is read.
The MIDI Port Operation Mode flag indicates whether the MIDI Port currently operates in Pass-Thru or UART mode. This
status flag is reflected by bit 4 of the MSTAT register. It can be used by software to keep track of the currently selected MIDI
Port operation mode.
6.2.8
MIDI Port Interrupts
The MIDI Port supports interrupt assertion in both Pass-Thru and UART modes, in response to one of the following events,
or both:
q
Receive Data Ready
q
Transmit Buffer Empty
The Receive Data Ready event refers to the case in which there is data to be read in the Receive Buffer/FIFO. An interrupt
request is asserted by the MIDI Port to indicate a Receive Data Ready event in one of the following cases:
The MIDI Port is in Pass-Thru mode, and the Receive Buffer contains a data or acknowledge byte which has not been
read yet. In this case, the interrupt request is deasserted once the Receive Buffer is read.
The MIDI Port is in UART mode, and the Receive FIFO contains eight, or more, data bytes which have not been read
yet, or it is in Pass-Thru mode with the Receive FIFO enabled. In this case, the interrupt request is deasserted once the
Receive FIFO level drops below eight bytes.
The MIDI Port is in UART mode, the Receive FIFO contains less than eight data bytes which have not been read yet,
and no data was received by the Communication Engine, the MIDI Port is in Pass-Thru mode with the Receive FIFO
enabled, or a read occurs from the Receive FIFO during a timeout period of approximately 1.28 msec (the time it takes
to transfer 4 bytes over the MIDI communication channel). In this case, the interrupt request is deasserted when either
new data is received by the Communication Engine, or data is read from the Receive FIFO.
The Transmit Buffer Empty event refers to the case in which the Transmit Buffer/FIFO of the MIDI Port can still accept data
to transmit. An interrupt request is asserted by the MIDI Port to indicate a Transmit Buffer Empty event in one of the following
cases:
The MIDI Port is in Pass-Thru mode, and the Transmit Buffer is empty. In this case, the interrupt request is deasserted
once a byte is written to the Transmit Buffer.
The MIDI Port is in UART mode, and the Transmit FIFO is empty. In this case, the interrupt request is deasserted once
the Transmit FIFO is filled with at least 3 bytes.
After hardware reset, interrupts are asserted by the MIDI Port only in response to a Receive Data Ready event. Interrupt
assertion in response to Transmit Buffer Empty events can be enabled by setting writing 1 to bit 1 of the MCNTL register.
Interrupt assertion in response to Receive Data Ready events can be disabled by writing 0 to bit 3 of the MCNTL register.
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相关代理商/技术参数 |
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| PC87393VJG | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:IC, SUPER I/O DEVICE, TQFP-100, Logic Device Type:Buffer, Supply Voltage Min:3V, |
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