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参数资料
| 型号： | PC87393F-VJG |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | 100-Pin LPC SuperI/O Devices for Portable Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 80/148页 |
| 文件大小： | 1733K |
| 代理商： | PC87393F-VJG |
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2.0 Device Architecture and Configuration (Continued)
37
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LPC-FWH Address Translation: The address field in the LPC-FWH transaction is constructed of eight nibbles. The first
seven nibbles correspond to the first LS seven address nibbles (A27-A0), as follows: the first incoming nibble corresponds
to addresses A27 - A24, the second to A23 - A20, and so forth until the seventh nibble, which corresponds to A3 - A0. In-
coming nibble eight is ignored. The MS bits of the 32-bit addresses are ’1111’ (A31 - A28).
2.8.2
CLKRUN Functionality
The PC8739x supports the CLKRUN I/O signal, whose use is highly recommended in portable systems. This signal is im-
plemented according to the specification in
PCI Mobile Design Guide, Revision 1.1, December 18, 1998. The PC8739x sup-
ports operation with both a slow and stopped clock in ACPI state S0 (the system is active but is not being accessed). The
PC8739x drives the CLKRUN signal low to force the LPC bus clock into full speed operation in the following cases:
q
An IRQ is pending internally, waiting to be sent through the serial IRQ.
q
A DMA request or abort is pending internally, waiting to be sent through the serial DMA.
Note: When the CLKRUN signal is not in use, the PC8739x assumes valid clock on the CLKIN pin.
2.8.3
LPCPD Functionality
The PC8739x supports the LPCPD input. This signal is used in case the VDD chip supply is not shared by all residents of
the LPC bus. The LPCPD signal conforms with Intel’s
LPC Interface Specification, Revision 1.00. Note that if the PC8739x
power supply exists while LPCPD is active, it is not mandatory to reset the PC8739x when LPCPD is de-asserted.
2.9
REGISTER TYPE ABBREVIATIONS
The following abbreviations are used to indicate the Register Type:
q
R/W = Read/Write
q
R = Read from a specic address returns the value of a specic register. Write to the same address is to a different
register.
q
W=Write
q
RO = Read Only
q
R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
2.10 SUPERI/O CONFIGURATION REGISTERS
This section describes the SuperI/O configuration and ID registers (those registers with first level indexes in the range of 20h
- 2Eh). See Table 15 for a summary and directory of these registers.
Note: Set the configuration registers to enable functions or signals that are relevant to the specific device. The val-
ues of fields that select functions, or signals, that are excluded from a specific device are treated as reserved and
should not be selected.
Table 15. SuperI/O Conguration Registers
Index
Mnemonic
Register Name
Power Well
Type
Section
20h
SID
SuperI/O ID
VDD
RO
21h
SIOCF1
SuperI/O Conguration 1
VDD
R/W
22h
SIOCF2
SuperI/O Conguration 2
VDD
R/W
23h
SIOCF3
SuperI/O Conguration 3
VDD
R/W
24h
SIOCF4
SuperI/O Conguration 4
VDD
R/W
25h
SIOCF5
SuperI/O Conguration 5
VDD
R/W
26h
SIOCF6
SuperI/O Conguration 6
VDD
R/W
27h
SRID
SuperI/O Revision ID
VDD
RO
28h
SIOCF8
SuperI/O Conguration 8
VDD
R/W
29h
SIOCF9
SuperI/O Conguration 9
VDD
R/W
2Ah
SIOCFA
SuperI/O Conguration A
VDD
R/W
2Bh - 2Fh
Reserved exclusively for National use
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相关代理商/技术参数 |
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| PC87393VJG | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:IC, SUPER I/O DEVICE, TQFP-100, Logic Device Type:Buffer, Supply Voltage Min:3V, |
| PC87393-VJG | 制造商:NSC 制造商全称:National Semiconductor 功能描述:100-Pin LPC SuperI/O Devices for Portable Applications |
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