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参数资料
| 型号： | PC87393F-VJG |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | 100-Pin LPC SuperI/O Devices for Portable Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 68/148页 |
| 文件大小： | 1733K |
| 代理商： | PC87393F-VJG |
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2.0
Device Architecture and Conguration
The PC8739x SuperI/O device comprises a collection of legacy and proprietary functional blocks. Each functional block is
described in a separate chapter in this document. However, some parameters in the implementation of each functional block
may vary per SuperI/O device. This chapter describes the PC8739x structure and provides all logical device specific infor-
mation, including special implementation of generic blocks, system interface and device configuration.
2.1
OVERVIEW
The PC8739x consists of 9 logical devices, the host interface, and a central set of configuration registers, all built around a
central, internal bus. The internal bus is similar to an 8-bit ISA bus protocol. See Figure 1, which illustrates the blocks and
related logic.
The system interface serves as a bridge between the external LPC interface and the internal bus. It supports 8-bit Read and
Write transactions for I/O, memory, DMA, and FWH, as defined in Intel’s
LPC Interface Specication, Revision 1.01.
The central configuration register set is ACPI compliant and supports a PnP configuration. The configuration registers are struc-
tured as a subset of the Plug and Play Standard registers, defined in Appendix A of the
Plug and Play ISA Specification, Re-
vision 1.0a by Intel and Microsoft. All system resources assigned to the functional blocks (I/O address space, DMA channels
and IRQ lines) are configured in, and managed by, the central configuration register set. In addition, some function-specific
parameters are configurable through the configuration registers and distributed to the functional blocks through special control
signals.
2.2
CONFIGURATION STRUCTURE AND ACCESS
The configuration structure is comprised of a set of banked registers which are accessed via a pair of specialized registers.
2.2.1
The Index-Data Register Pair
Access to the SuperI/O configuration registers is via an Index-Data register pair, using only two system I/O byte locations.
The base address of this register pair is determined during reset, according to the state of the hardware strapping option on
the BADDR pin. Table 5 shows the selected base addresses as a function of BADDR.
Table 5. BADDR Strapping Options
The Index register is an 8-bit read/write register located at the selected base address (Base+0). It is used as a pointer to the
configuration register file, and holds the index of the configuration register that is currently accessible via the Data register.
Reading the Index register returns the last value written to it (or the default of 00h after reset).
The Data register is an 8-bit register (Base+1) used as a data path to any configuration register. Accessing the Data register
actually accesses the configuration register that is currently pointed to by the Index register.
BADDR
I/O Address
Index Register
Data Register
0
2Eh
2Fh
1
4Eh
4Fh
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相关代理商/技术参数 |
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| PC87393VJG | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:IC, SUPER I/O DEVICE, TQFP-100, Logic Device Type:Buffer, Supply Voltage Min:3V, |
| PC87393-VJG | 制造商:NSC 制造商全称:National Semiconductor 功能描述:100-Pin LPC SuperI/O Devices for Portable Applications |
| PC87410 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PC87410 PCI-IDE Interface Controller |
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| PC87413 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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