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参数资料
| 型号： | PC87393F-VJG |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | 100-Pin LPC SuperI/O Devices for Portable Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 121/148页 |
| 文件大小： | 1733K |
| 代理商： | PC87393F-VJG |
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3.0 General-Purpose Input/Output (GPIO) Port (Continued)
74
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3.3
EVENT HANDLING AND SYSTEM NOTIFICATION
The enhanced GPIO port supports system notification based on event detection. This functionality is based on six configu-
ration bits and a bit slice of runtime registers GPEVEN and GPEVST. The configuration and operation of the event detection
capability is shown in Figure 10. The operation of system notification is illustrated in Figure 11.
Figure 10. Event Detection
3.3.1
Event Configuration
Each pin in the GPIO port is a potential input event source. The event detection can trigger a system notification upon pre-
determined behavior of the source pin. The GPCFG register determines the event detection trigger type for the system no-
tification.
Event Type and Polarity
Two trigger types of event detection are supported: edge and level. An edge event may be detected upon a source pin tran-
sition either from high to low or low to high. A level event may be detected when the source pin is in active level. The trigger
type is determined by Event Type (bit 4 of the GPCFG register). The direction of the transition (for edge) or the polarity of
the active level (for level) is determined by Event Polarity (bit 5 of the GPCFG register).
Event Debounce Enable
The input signal can be debounced for about 15 msec before entering the detector. The signal state is transferred to the
detector only after a debouncing period during which the signal has no transitions, to ensure that the signal is stable. The
debouncer adds 15 msec delay to both assertion and de-assertion of the event pending indicator. Therefore, when working
with a level event and system notification by either SMI or IRQ, it is recommended to disable the debounce if the delay in
the SMI/IRQ de-assertion is not acceptable. The debounce is controlled by Event Debounce Enable (bit 6 of the GPCFG
register).
3.3.2
System Notification
System notification on GPIO-triggered events is by means of assertion of one or more of the following output pins:
q
Interrupt Request (via the device’s Bus Interface)
q
System Management Interrupt (SMI, via the device’s Bus Interface)
The system notication for each GPIO pin is controlled by the corresponding bits in the GPEVEN and GPEVR registers.
System notification by a GPIO pin is enabled if the corresponding bit of the GPEVEN register is set to 1. The corresponding
bits in the GPEVR register select which means of system notification the detected event is routed to. The event routing
mechanism is described in Figure 11.
Event
Enable
Event Polarity
Detected
Enabled Events
GPIO Pins
Input
Debouncer
1
0
Event
Internal
Bus
0
1
Pin
Level =1
R/W 1 to Clear
Status
Rising Edge or
Rising
Edge
Detector
from other
High Level =1
GPIO Pin Conguration Register
Event Type
Event
Debounce
Enable
R/W
Bit 6
Bit 5
Bit 4
Indicator
Pending
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相关代理商/技术参数 |
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|---|---|
| PC87393VJG | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:IC, SUPER I/O DEVICE, TQFP-100, Logic Device Type:Buffer, Supply Voltage Min:3V, |
| PC87393-VJG | 制造商:NSC 制造商全称:National Semiconductor 功能描述:100-Pin LPC SuperI/O Devices for Portable Applications |
| PC87410 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PC87410 PCI-IDE Interface Controller |
| PC87410VLK | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87413 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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