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参数资料
| 型号： | RN80532KC0412M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2000 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | Interposer, Micro, PGA-603 |
| 文件页数： | 24/132页 |
| 文件大小： | 2316K |
| 代理商： | RN80532KC0412M |
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Introduction
1-2
Intel Xeon Processor MP with up to 2MB L3 Cache
As a note of reference, the Intel Xeon processor with 512-KB L2 cache on the 0.13 micron
process in the FC-mPGA2 package contains an extra pin (located at location AE30) compared to
the INT-mPGA package. This additional pin serves as a keying mechanism to prevent the FC-
mPGA2 package from being installed in the 603-pin socket since processors in the FC-mPGA2
package are only supported in the 604-pin socket. Since the additional contact for pin AE30 is
electrically inert, the 604-pin socket will not have a solder ball at this location.
Mechanical components used for attaching thermal solutions to the baseboard should have a high
degree of commonality with the thermal solution components enabled for the Intel Xeon processor.
Enabled heatsinks and retention mechanisms have been designed with manufacturability as a high
priority. Hence, mechanical assembly can be completed from the top of the baseboard.
The Intel Xeon processor MP on the 0.13 micron process uses a scalable system bus protocol
referred to as the “system bus” in this document. This processor system bus utilizes a split-
transaction, deferred reply protocol similar to that of the P6 processor family system bus, but is not
compatible with the P6 processor family system bus. This processor system bus is compatible with
the Intel Xeon processor system bus. The system bus uses Source-Synchronous Transfer (SST) of
address and data to improve performance. Whereas the P6 processor family transfers data once per
bus clock, the Intel Xeon processor MP on the 0.13 micron process processor transfers data four
times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address
bus can deliver addresses two times per bus clock and is referred to as a ‘double-clocked’ or 2X
address bus. In addition, the Request Phase completes in one clock cycle. Working together, the 4X
data bus and 2X address bus provide a data bus bandwidth of up to 3.2 GB/second (3200 MB/sec)
with a 400 MHz system bus. Finally, the system bus also introduces transactions that are used to
deliver interrupts.
Signals on the system bus use Assisted GTL+ (AGTL+) level voltages which are fully described in
the appropriate platform design guide (refer to Section 1.2).
Table 1.
Feature Table for Intel Xeon Processor MP on the 0.13 Micron Process
#
of
Su
ppor
te
d
Sym
m
etri
c
Ag
en
ts
L
2
Ad
van
ced
T
ra
n
sfe
r
Ca
ch
e
Int
e
gr
a
te
d
L
3
Cach
e
System
Bu
s
Fr
e
q
ue
nc
y
S
M
Bu
s
F
eat
u
res
In
tel
Net
B
u
rst
M
icr
oa
rc
hi
tec
tu
re
In
te
l
Hyp
e
r-
T
h
re
a
d
in
g
T
e
ch
no
lo
gy
P
ackag
e
S
o
cket
Intel
Xeon
processor
MP with
up to 2-
MB L3
cache
1 - 4
512 KB
1MB, 2
MB
400 MHz
Yes
INT-
mPGA
(603 pins)
603-pin
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RN80532KC041512 | 制造商:Intel 功能描述:TRAY XEON 2.0GHZ 400MZH FSB - Trays 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RN80532KC041512 SL5Z9 | 制造商:Intel 功能描述:MPU XEON 0.13UM 2GHZ 603-PIN UFCBGA - Trays |
| RN80532KC041512 SL6EM | 制造商:Intel 功能描述:MPU XEON 0.13UM 2GHZ 603-PIN UFCBGA - Trays |
| RN80532KC041512S L5Z9 | 制造商:Intel 功能描述:MPU Xeon? Processor 0.13um 2GHz 603-Pin uFCBGA |
| RN80532KC041512S L6W6 | 制造商:Intel 功能描述:MPU Xeon? Processor 0.13um 2GHz 603-Pin uFCBGA |
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