
Intel Xeon Processor MP with up to 2MB L3 Cache
2-3
Electrical Specifications
clock. Details regarding BCLK[1:0] driver specifications are provided in the CK00 Clock
Synthesizer/Driver Design Guidelines.
Table 2 contains Intel Xeon processor MP on the 0.13
micron process processor bus fraction ratios and their corresponding core frequencies.
NOTES:
1. Individual processors operate only at or below the frequency marked on the package.
2. Listed frequencies are not necessarily committed production frequencies.
3. Platforms should support a 400 MHz system bus.
2.4.1
Bus Clock
The system bus frequency is set to the maximum supported by the individual processor. BSEL[1:0]
are outputs used to select the system bus frequency.
Table 3 defines the possible combinations of
the signals and the frequency associated with each combination. The frequency is determined by
the processor(s), chipset, and clock synthesizer. All system bus agents must operate at the same
frequency. Individual processors will only operate at their specified system bus clock frequency.
The Intel Xeon processor with a 400 MHz system bus is designed to run on a baseboard with a
100 MHz bus clock. On these baseboards, BSEL[1:0] are both considered ‘reserved’ at the
processor socket. No change is required for operation with Intel Xeon processor MP on the 0.13
micron process processors. Operation will default to 100 MHz.
See the appropriate platform design guide for further details.
Table 2.
Core Frequency to System Bus Multiplier Configuration
Core Frequency to System Bus
Multiplier Configuration
Core Frequency 100 MHz BCLK
Notes1,2,3
1/12
1.20 GHz
1/13
1.30 GHz
1/14
1.40 GHz
1/15
1.50 GHz
1/16
1.60 GHz
1/17
1.70 GHz
1/18
1.80 GHz
1/19
1.90 GHz
1/20
2 GHz
1/25
2.5 GHz
1/28
2.8 GHz
Table 3.
System Bus Clock Frequency Select Truth Table for BSEL[1:0]
BSEL1
BSEL0
Bus Clock Frequency
0
100 MHz
01
Reserved
10
Reserved
11
Reserved