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参数资料
| 型号： | RN80532KC0412M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2000 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | Interposer, Micro, PGA-603 |
| 文件页数： | 48/132页 |
| 文件大小： | 2316K |
| 代理商： | RN80532KC0412M |
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Electrical Specifications
2-8
Intel Xeon Processor MP with up to 2MB L3 Cache
2.7
Reserved or Unused Pins
All Reserved pins must remain unconnected on the system baseboard. Connection of these pins to
V
CC, VSS, or to any other signal (including each other) can result in component malfunction or
incompatibility with future processors. See Section 9 for a pin listing of the processor and for the
location of all Reserved pins.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. In a system level design, on-die termination has been included on the Intel Xeon
processor MP on the 0.13 micron process processor to allow signals to be terminated within the
processor silicon. Most unused AGTL+ inputs should be left as no connects, as AGTL+ termination
is provided on the processor silicon. However, see Table 4 for details on AGTL+ signals that do not
include on-die termination. Unused active high inputs should be connected through a resistor to
ground (VSS). Unused outputs can be left unconnected, however this may interfere with some TAP
functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used
when tying bidirectional signals to power or ground. When tying any signal to power or ground, a
resistor will also allow for system testability. For unused AGTL+ input or I/O signals, use pull-up
resistors of the same value for the on-die termination resistors (R
TT). See Table 14.
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and all used outputs must be terminated on the baseboard. Unused outputs may
be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated
may interfere with some TAP functions, complicate debug probing, and prevent boundary scan
testing.
All TESTHI[6:0] pins should be individually connected to V
CC via a pull-up resistor which
matches the trace impedance within a range of ± 10
. TESTHI[3:0] and TESTHI[6:5] may all be
tied together and pulled up to V
CC with a single resistor if desired. However, utilization of boundary
scan test will not be functional if these pins are connected together. TESTHI4 must always be
pulled up independently from the other TESTHI pins. For optimum noise margin, all pull-up
resistor values used for TESTHI[6:0] pins should have a resistance value within ± 20% of the
impedance of the baseboard transmission line traces. For example, if the trace impedance is 50
,
then a value between 40
and 60 should be used. The TESTHI[6:0] termination
recommendations provided in the Intel Xeon Processor MP Datasheet are still suitable for the
Intel Xeon processor MP on the 0.13 micron process processor. However, Intel recommends new
designs or designs undergoing design updates follow the trace impedance matching termination
guidelines given in this section.
2.8
System Bus Signal Groups
In order to simplify the following discussion, the system bus signals have been combined into
groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as
a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+
output group as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals whose timings are specified with respect to
rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source
synchronous signals which are relative to their respective strobe lines (data and address) as well as
the rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can
become active at any time during the clock cycle. Table 5 identifies which signals are common
clock, source synchronous and asynchronous.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RN80532KC041512 | 制造商:Intel 功能描述:TRAY XEON 2.0GHZ 400MZH FSB - Trays 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RN80532KC041512 SL5Z9 | 制造商:Intel 功能描述:MPU XEON 0.13UM 2GHZ 603-PIN UFCBGA - Trays |
| RN80532KC041512 SL6EM | 制造商:Intel 功能描述:MPU XEON 0.13UM 2GHZ 603-PIN UFCBGA - Trays |
| RN80532KC041512S L5Z9 | 制造商:Intel 功能描述:MPU Xeon? Processor 0.13um 2GHz 603-Pin uFCBGA |
| RN80532KC041512S L6W6 | 制造商:Intel 功能描述:MPU Xeon? Processor 0.13um 2GHz 603-Pin uFCBGA |
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