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参数资料
型号： RN80532KC0412M
厂商： INTEL CORP
元件分类： 微控制器/微处理器
英文描述： 2000 MHz, MICROPROCESSOR, CPGA603
封装： Interposer, Micro, PGA-603
文件页数： 49/132页
文件大小： 2316K
代理商： RN80532KC0412M
Intel Xeon Processor MP with up to 2MB L3 Cache
2-9
Electrical Specifications
NOTES:
1. Refer to Section 9.2 for signal descriptions.
2. These signal groups are not terminated by the processor.
3. These signals do not have on-die termination. Refer to corresponding platform design guidelines for
termination requirements.
4. Note that Reset initialization function of these pins is now a software function on the Intel Xeon
processor MP on the 0.13 micron process processor.
5. The value of these pins during the active-to-inactive edge of RESET# to determine processor configuration
options. See Section 6.1 for details.
6. These signals may be driven simultaneously by multiple agents (wired-or).
7. These signals are not terminated by the processor’s on-die termination. However, some signals in this group
include termination on the processor interposer. See Section 6.4 for details.
8. SM_Vcc is required for correct operation of the Intel Xeon processor MP on the 0.13 micron process
processors VID logic. Refer to Figure 18 for details.
2.9
Asynchronous GTL+ Signals
The Intel Xeon processor MP on the 0.13 micron process processor does not utilize CMOS voltage
levels on any signals that connect to the processor silicon. As a result, legacy input signals such as
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# utilize GTL+
Table 5.
System Bus Signal Groups
Signal Group
Type
Signals 1
AGTL+ Common Clock Input
Synchronous to BCLK[1:0]
BPRI#, BR[3:1]#3, DEFER#, RESET#3,
RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0]
ADS#, AP[1:0]#, BINIT#6, BNR#6,
BPM[5:0]#2, BR0#2, DBSY#, DP[3:0]#,
DRDY#, HIT#6, HITM#6, LOCK#, MCERR#6
AGTL+ Source Synchronous
I/O
Synchronous to assoc.
strobe
AGTL+ Strobes
Synchronous to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Asynchronous GTL+ Input 3
Asynchronous
A20M#4, IGNNE#4, INIT#5, LINT0/INTR4,
LINT1/NMI4, SMI#5, SLP#, STPCLK#
Asynchronous GTL+ Output 3
Asynchronous
FERR#, IERR#, THERMTRIP#, PROCHOT#
System Bus Clock
Clock
BCLK1, BCLK0
TAP Input 2
Synchronous to TCK
TCK, TDI, TMS, TRST#
TAP Output 2
Synchronous to TCK
TDO
SMBus Interface 7
Synchronous to SM_CLK
SM_EP_A[2:0], SM_TS_A[1:0], SM_DAT,
SM_CLK, SM_ALERT#, SM_WP
Power/Other
BSEL[1:0], COMP[1:0], GTLREF, ODTEN,
PWRGOOD, Reserved, SKTOCC#,
TESTHI[6:0],VID[4:0], VCC, SM_VCC
8, V
CCA ,
VCCIOPLL, VSSA, , VSS, VCCSENSE, VSSSENSE
Signals
Associated Strobe
REQ[4:0]#,A[16:3]#5
ADSTB0#
A[35:17]#4
ADSTB1#
D[15:0]#, DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DBI3#
DSTBP3#, DSTBN3#
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