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| 型号： | RN80532KC0412M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2000 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | Interposer, Micro, PGA-603 |
| 文件页数： | 27/132页 |
| 文件大小： | 2316K |
| 代理商： | RN80532KC0412M |
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9-24
Intel Xeon Processor MP with up to 2MB L3 Cache
LINT[1:0]
I
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all system
bus agents. When the APIC functionality is disabled, the LINT0 signal becomes
INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a
nonmaskable interrupt. INTR and NMI are backward compatible with the signals of
those names on the Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK#
I/O
LOCK# indicates to the system that a transaction must occur atomically. This signal
must connect the appropriate pins of all processor system bus agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
MCERR#
I/O
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor system bus
agents.
MCERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:
Enabled or disabled.
Asserted, if configured, for internal errors along with IERR#.
Asserted, if configured, by the request initiator of a bus transaction after it
observes an error.
Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, refer to the IA-32 Software
Developer’s Manual, Volume 3: System Programming Guide
.
Since multiple agents may drive this signal at the same time, MCERR# is a wire-OR
signal which must connect the appropriate pins of all processor system bus agents.
In order to avoid wire-OR glitches associated with simultaneous edge transitions
driven by multiple drivers, MCERR# is activated on specific clock edges and
sampled on specific clock edges.
ODTEN
I
ODTEN (On-die termination enable) should be connected to VCC to enable on-die
termination for end bus agents. For middle bus agents, pull this signal down via a
resistor to ground to disable on-die termination. Whenever ODTEN is high, on-die
termination will be active, regardless of other states of the bus.
PROCHOT#
O
The assertion of PROCHOT# (processor hot) indicates that the processor die
temperature has reached its thermal limit. See Section 6.3 for more details.
These signals do not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
PWRGOOD
I
PWRGOOD (Power Good) is an input. The processor requires this signal to be a
clean indication that all Intel Xeon processor MP on the 0.13 micron process
processor clocks and power supplies are stable and within their specifications.
“Clean” implies that the signal will remain low (capable of sinking leakage current),
without glitches, from the time that the power supplies are turned on until they come
within specification. The signal must then transition monotonically to a high state.
Figure 12 illustrates the relationship of PWRGOOD to the RESET# signal.
PWRGOOD can be driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD. It must also meet the
minimum pulse width specification in Table 18, and be followed by a 1 ms RESET#
pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
Table 52. Signal Definitions (Sheet 6 of 9)
Name
Type
Description
相关PDF资料 |
PDF描述 |
|---|---|
| RN80532KC041512 | 32-BIT, 2000 MHz, MICROPROCESSOR, CPGA603 |
| RP0352 | GRAPHICS PROCESSOR, PQFP80 |
| RP65C02G-06 | 8-BIT, 6 MHz, MICROPROCESSOR, PDIP40 |
| RPIXP2800BC | 32-BIT, 650 MHz, RISC PROCESSOR, PBGA1356 |
| RPIXP2850BB | 32-BIT, 1400 MHz, RISC PROCESSOR, PBGA1356 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| RN80532KC041512 | 制造商:Intel 功能描述:TRAY XEON 2.0GHZ 400MZH FSB - Trays 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RN80532KC041512 SL5Z9 | 制造商:Intel 功能描述:MPU XEON 0.13UM 2GHZ 603-PIN UFCBGA - Trays |
| RN80532KC041512 SL6EM | 制造商:Intel 功能描述:MPU XEON 0.13UM 2GHZ 603-PIN UFCBGA - Trays |
| RN80532KC041512S L5Z9 | 制造商:Intel 功能描述:MPU Xeon? Processor 0.13um 2GHz 603-Pin uFCBGA |
| RN80532KC041512S L6W6 | 制造商:Intel 功能描述:MPU Xeon? Processor 0.13um 2GHz 603-Pin uFCBGA |
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