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| 型号： | W9725G8JB-25I |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA84 |
| 封装： | 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84 |
| 文件页数： | 15/86页 |
| 文件大小： | 1462K |
| 代理商： | W9725G8JB-25I |
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W9725G8JB
Publication Release Date: Oct. 12, 2010
- 22 -
Revision A01
7.3.8
Self Refresh Exit Command
(CKE = "H", CS = "H" or CKE = "H", CS = "L", RAS = "H", CAS = "H", WE = "H", BA0, BA1,
A0 to A12 = Don
t Care)
The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be
stable prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least tXSNR
must be satisfied before a valid command can be issued to the device to allow for any internal refresh
in progress. CKE must remain HIGH for the entire Self Refresh exit period tXSRD for proper operation
except for self refresh re-entry.
Upon exit from Self Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after waiting
at least tXSNR period and issuing one refresh command (refresh period of tRFC). NOP or Deselect
commands must be registered on each positive clock edge during the Self Refresh exit interval tXSNR.
ODT should be turned off during tXSRD.
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be
missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2
SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh
mode.
7.3.9
Refresh Command
( CS = "L", RAS = "L", CAS = "L", WE = "H", CKE = "H", BA0, BA1, A0 to A12 = Dont Care)
Refresh is used during normal operation of the DDR2 SDRAM. This command is non persistent, so it
must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address
bits
”Dont Care” during an Auto Refresh command. The DDR2 SDRAM requires Auto Refresh cycles
at an average periodic interval of
tREFI (max.).
When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle)
state. A delay between the auto refresh command (REF) and the next activate command or
subsequent auto refresh command must be greater than or equal to the auto refresh cycle time (tRFC).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of eight Refresh commands can be posted to any
given DDR2 SDRAM, meaning that the maximum absolute interval between any Refresh command
and the next Refresh command is 9 x tREFI.
T0
T1
T2
T3
CLK/CLK
CKE
CMD
≥ tRP
≥ tRFC
NOP
ANY
REF
Precharge
"HIGH"
Tm
Tn
Tn + 1
Figure 13
– Refresh command
相关PDF资料 |
PDF描述 |
|---|---|
| W972GG8JB-25I | 256M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| W972GG8JB-18 | 256M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| W9751G6JB-18 | 32M X 16 DDR DRAM, 0.35 ns, PBGA84 |
| W981204AH-8H | 32M X 4 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| W981216BH75L | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W9725G8JB25ITR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X8, IND TEMP |
| W9725G8JB25TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X8 |
| W9725G8KB-18 | 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9725G8KB-25 | 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9725G8KB-25 TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X8 |
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