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| 型号： | W9725G8JB-25I |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA84 |
| 封装： | 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84 |
| 文件页数： | 51/86页 |
| 文件大小： | 1462K |
| 代理商： | W9725G8JB-25I |
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W9725G8JB
Publication Release Date: Oct. 12, 2010
- 55 -
Revision A01
43. tIS and tIH (input setup and hold) derating.
tIS/tIH Derating values for DDR2-667, DDR2-800 and DDR2-1066
Command/
Address
Slew Rate
(V/nS)
ΔtIS and ΔtIH Derating Values for DDR2-667, DDR2-800 and DDR2-1066
CLK/ CLK Differential Slew Rate
2.0 V/nS
1.5 V/nS
1.0 V/nS
Unit
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
4.0
+150
+94
+180
+124
+210
+154
pS
3.5
+143
+89
+173
+119
+203
+149
pS
3.0
+133
+83
+163
+113
+193
+143
pS
2.5
+120
+75
+150
+105
+180
+135
pS
2.0
+100
+45
+130
+75
+160
+105
pS
1.5
+67
+21
+97
+51
+127
+81
pS
1.0
0
+30
+60
pS
0.9
-5
-14
+25
+16
+55
+46
pS
0.8
-13
-31
+17
-1
+47
+29
pS
0.7
-22
-54
+8
-24
+38
+6
pS
0.6
-34
-83
-4
-53
+26
-23
pS
0.5
-60
-125
-30
-95
0
-65
pS
0.4
-100
-188
-70
-158
-40
-128
pS
0.3
-168
-292
-138
-262
-108
-232
pS
0.25
-200
-375
-170
-345
-140
-315
pS
0.2
-325
-500
-295
-470
-265
-440
pS
0.15
-517
-708
-487
-678
-457
-648
pS
0.1
-1000
-1125
-970
-1095
-940
-1065
pS
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and
tIH(base) value to the ΔtIS and ΔtIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between
shaded VREF(dc) to AC region, use nominal slew rate for derating value. See Figure 20 Illustration of nominal slew rate for tIS.
If the actual signal is later than the nominal slew rate line anywhere between shad
ed VREF(dc) to AC region, the slew rate of a
tangent line to the actual signal from the AC level to DC level is used for derating value. See Figure 21 Illustration of tangent line
for tIS.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first
crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between
shaded DC to VREF(dc) region, use nominal slew rate for derating value. See Figure 22 Illustration of nominal slew rate for tIH.
If the actual signal is earlier than the
nominal slew rate line anywhere between shaded DC to VREF(dc) region, the slew rate of
a tangent line to the actual signal from the DC level to VREF(dc) level is used for derating value. See Figure 23 Illustration of
tangent line for tIH.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at
the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in above tIS/tIH derating values for DDR2-667, DDR2-800 and DDR2-1066 table, the
derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9725G8JB25ITR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X8, IND TEMP |
| W9725G8JB25TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X8 |
| W9725G8KB-18 | 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9725G8KB-25 | 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9725G8KB-25 TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X8 |
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