参数资料
型号: W9725G8JB-25I
厂商: WINBOND ELECTRONICS CORP
元件分类: DRAM
英文描述: DDR DRAM, PBGA84
封装: 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84
文件页数: 7/86页
文件大小: 1462K
代理商: W9725G8JB-25I
W9725G8JB
Publication Release Date: Oct. 12, 2010
- 15 -
Revision A01
7.2.3
Off-Chip Driver (OCD) Impedance Adjustment
DDR2 SDRAM supports driver calibration feature and the flow chart in Figure 6 is an example of the
sequence. Every calibration mode command should be followed by “OCD calibration mode exit”
before any other command being issued. MRS should be set before entering OCD impedance
adjustment and On Die Termination (ODT) should be carefully controlled depending on system
environment.
Start
ALL OK
All MR shoud be programmed before entering OCD impedance adjustment and ODT should
be carefully controlled depending on system environment
EMRS: Drive(0)
DQ &DQS Low; DQS High
EMRS: OCD calibration mode exit
Test
Need Calibration
EMRS: OCD calibration mode exit
EMRS:
Enter Adjust Mode
BL=4 code input to all DQs
Inc, Dec or NOP
EMRS: OCD calibration mode exit
ALL OK
EMRS: Drive(1)
DQ &DQS High; DQS Low
Test
Need Calibration
EMRS: OCD calibration mode exit
EMRS:
Enter Adjust Mode
BL=4 code input to all DQs
Inc, Dec or NOP
EMRS: OCD calibration mode exit
End
Figure 6
– OCD Impedance Adjustment Flow Chart
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