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参数资料
| 型号： | W9725G8JB-25I |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA84 |
| 封装： | 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84 |
| 文件页数： | 4/86页 |
| 文件大小： | 1462K |
| 代理商： | W9725G8JB-25I |
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W9725G8JB
Publication Release Date: Oct. 12, 2010
- 12 -
Revision A01
7.2.2.2
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization,
and upon returning to normal operation after having the DLL disabled. The DLL is automatically
disabled when entering Self Refresh operation and is automatically re-enabled and reset upon exit of
Self Refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must
occur before a Read command can be issued to allow time for the internal clock to be synchronized
with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC
or tDQSCK parameters.
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
OCD program
BT
Rtt
Address Field
Extended Mode Register (1)
BA1
BA0
MRS mode
0
1
MRS
EMR (1)
EMR (2)
EMR (3)
A6
A2
0
1
WR
Additive Latency
Qoff
RDQS
DQS
Rtt
D.I.C
DLL
Rtt (nominal)
ODT disabled
75 ohm
150 ohm
50 ohm*
1
0
A0
1
DLL Enable
Enable
Disable
OCD Calibration Program
OCD calibration mode exit; matain setting
Adjust mode*
2
OCD Calibration default*
3
Drive (1)
Drive (0)
A9
A8
A7
1
0
1
0
Driver impedance adjustment
A12
1
0
Output buffer enabled
Qoff
Output buffer disabled
A10
1
0
DQS
Enable
Disable
Output driver
impedance control
Reduced
Normal
A1
0
1
A5
0
1
A4
0
1
0
1
A3
0
1
0
1
0
1
0
Latency
0
3
4
Resesved
6
1
2
Driver strength control
Driver size
100%
60%
5
Additive Latency
BA1
BA0
A11
1
0
RDQS Enable*
4
Disable
Enable
A10
(DQS Enable)
0 (Enable)
1 (Disable)
0 (Enable)
1 (Disable)
0 (Disable)
1 (Enable)
A11
(RDQS Enable)
Strobe Function Matrix
DQS
DQS
DQS
DQS
Hi-z
RDQS/DM
RDQS
DQS
Hi-z
DQS
Hi-z
RDQS
Hi-z
DM
RDQS
D
R
2
-6
6
7
/8
0
D
R
2
-1
0
6
Notes:
1. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066.
2. When Adjust mode is issued, AL from previously set value must be applied.
3. After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. Refer to the section 7.2.3 for
detailed information.
4. If RDQS is enabled, the DM
function is disabled. RDQS is active for reads and dont care for writes.
Figure 3
– EMR (1)
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PDF描述 |
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| W972GG8JB-25I | 256M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| W972GG8JB-18 | 256M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| W9751G6JB-18 | 32M X 16 DDR DRAM, 0.35 ns, PBGA84 |
| W981204AH-8H | 32M X 4 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| W981216BH75L | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W9725G8JB25ITR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X8, IND TEMP |
| W9725G8JB25TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X8 |
| W9725G8KB-18 | 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9725G8KB-25 | 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9725G8KB-25 TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X8 |
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