PRELIMINARY
XRT79L71
178
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
4.3
THE RECEIVE DIRECTION
The next several sections will present an in-depth functional description of the all of the blocks that are
operating in the Receive Direction, within the XRT79L71, when configured to operate in the Clear-Channel
DS3 Framer Mode.
Figure 81 presents a functional block diagram of the XRT79L71 Receive Direction
circuitry.
Figure 81 indicates that the Receive Direction circuitry consists of the following functional blocks.
The Receive DS3 LIU block
The Receive DS3 Framer block
The Receive FEAC Processor block
The Receive LAPD Controller block
The Receive Payload Data Output Interface block
The Receive Overhead Data Output Interface block
4.3.1
RECEIVE DS3 LIU BLOCK
The Receive DS3/E3 LIU Block is the very first functional block within the Receive Direction of the XRT79L71
that we will discuss for Clear-Channel Framer Applications. Figure 82 presents an illustration of the Receive
Direction circuitry whenever the XRT79L71 has been configured to operate in the DS3 Clear-Channel Framer
Mode, with the Receive DS3/E3 LIU block highlighted.
FIGURE 81. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY WHEN-
EVER THE
XRT79L71 HAS BEEN CONFIGURED TO OPERATE IN THE DS3 CLEAR-CHANNEL FRAMER MODE
Receive
Payload Data
Output
Interface
Block
Receive
Payload Data
Output
Interface
Block
Receive
DS3/E3
Framer
Block
Receive
DS3/E3
Framer
Block
Receive
DS3/E3
LIU Block
Receive
DS3/E3
LIU Block
RxSer
RxNib[3:0]
RxClk
RRING
RTIP
Receive
Overhead Data
Output Interface
Block
Receive
Overhead Data
Output Interface
Block
RxOHClk
RxOHInd
RxOH
RxOHEnable
RxOHFrame
RxNibClk
RxFrame
Rx LAPD
Controller
Block
Rx LAPD
Controller
Block
From Microprocessor
Interface Block
Rx LAPD
Buffer
(90 Bytes)
Rx LAPD
Buffer
(90 Bytes)
Rx FEAC
Processor
Block
Rx FEAC
Processor
Block