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PRELIMINARY
XRT79L71
78
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
Configuring the XRT79L71 to operate in Mode 2 (Serial/Local-Timing/Frame-Slave Mode)
The user can configure the XRT79L71 to operate in Mode 2 by executing the following steps.
STEP 1 - Design your board such that the System-Side Terminal Equipment circuitry interfaces to the
Transmit Payload Data Input Interface in the manner as depicted above in Figure 32. STEP 2 - Configure the XRT79L71 to operate in the Serial Mode
This can be accomplished by setting the NibIntf input pin to a logic "Low".
STEP 3 - Configure the XRT79L71 to operate in the Local-Timing/Frame Slave Mode
This can be accomplished by setting Bits 1 and 0 (TimRefSel[1:0]) within the Framer Operating Mode Register
to [0, 1] as depicted below.
4.2.1.3
Mode 3 - Serial/Local-Timing/Frame Master Mode Operation of the Transmit Payload Data
Input Interface Block
If the XRT79L71 is configured to operate in Mode 3 then all of the following is true.
FIGURE 33. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE
2 (SERIAL/LOCAL-TIMING/FRAME-SLAVE) MODE OPERATION
Framer Operating Mode Register (Address = 0x1100)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Local Loop
Back
IsDS3
Internal LOS
Enable
RESET
Direct
Mapped
ATM
Frame For-
mat
TimRefSel[1:0]
R/W
0
1
0
1
0
1
System-Side Terminal Equipment Signals
DS3_Clock_In
DS3_Data_Out
Tx_Start_of_Frame
DS3_Overhead_Ind
XRT79L71 Transmit Payload Data Input Interface Signals
TxInClk
TxSer
TxFrameRef
TxOH_Ind
Payload[4702]
Payload[4703]
X-Bit
Payload[1]
Payload[4702]
Payload[4703]
X-Bit
Payload[1]
Note: X-Bit will not be processed by the
Transmit Payload Data Input Interface.
DS3 Frame Number N
DS3 Frame Number N + 1
Note: TxFrame pulses high to denote
DS3 Frame Boundary.
Note: TxOH_Ind pulses high to
denote Overhead Data
(e.g., the X-bit).