
PRELIMINARY
XRT79L71
324
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
STEP 1 - Set Bit 7 (TxBIP-4 Enable), within the "Transmit E3 Configuration" Register, to "0" as depicted
below.
STEP 2 - Set Bit 0 (RxBIP-4 Enable), within the "Receive E3 Configuration and Status Register # 1" to
"0", as depicted below.
STEP 3 - Set Bit 1 (TxA), within the "Transmit E3 Service Bits" Register, to "1" as depicted below.
STEP 4 - Set Bit 5 and 6 (TxASrcSel[1:0]) within the "Transmit E3 Configuration" Register, to "[0, 0]" as
depicted below.
This step configures the Transmit E3 Framer block to read out the contents of Bit 1 (TxA) within the "Transmit
E3 Service Bits" Register, as set the "A" bit (within each outbound E3 frame) to this value.
In this case, since we have set Bit 1 (TxA) within the "Transmit E3 Service Bits" Register to "1", then the
Transmit E3 Framer block will now set the "A" bit-field (within each outbound E3 frame) to "1" (denoting the
FERF/RDI indication).
5.2.4.4
TRANSMITTING THE FEBE/REI (FAR-END BLOCK ERROR/REMOTE ERROR) INDICATOR
Transmit E3 Configuration Register - G.751 (Address = 0x1130)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxBIP-4
Enable
TxASrcSel[1:0]
TxNSrcSel[1:0]
TxAIS
Enable
TxLOS
Enable
TxFAS
Source Sel
R/W
0
Receive E3 Configuration and Status Register # 1 - G.751 (Address = 0x1110)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
RxFERFAlgo
Unused
RxBIP-4
Enable
R/O
R/W
R/O
R/W
0
Transmit E3 Service Bits Register - G.751 (Address = 0x1135)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
TxA
TxN
R/O
R/W
0
1
0
Transmit E3 Configuration Register - G.751 (Address = 0x1130)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxBIP-
4Enable
TxASrc-
Sel[1:0]
TxNSrc-
Sel[1:0]
TxAIS
Enable
TxLOS
Enable
TxFASSou-
rceSel
R/W
0